CY8C5246LTI-029(2011_03) 查看數據表（PDF） - Cypress Semiconductor

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CY8C5246LTI-029
(Rev.:2011_03)

Programmable System-on-Chip (PSoC®)

Cypress Semiconductor 

PRELIMINARY

PSoC® 5: CY8C52 Family Datasheet

VDDD. Supply for all digital peripherals and digital core regulator.

VDDD must be less than or equal to VDDA.

VSSA. Ground for all analog peripherals.

VSSB. Ground connection for boost pump.

VSSD. Ground for all digital logic and I/O pins.

VDDIO0, VDDIO1, VDDIO2, VDDIO3. Supply for I/O pins. Each

VDDIO must be tied to a valid operating voltage (1.71 V to 5.5 V),

and must be less than or equal to VDDA. If the I/O pins associated

with VDDIO0, VDDIO2 or VDDIO3 are not used then that VDDIO

should be tied to ground (VSSD or VSSA).

XRES. External reset pin. Active low with internal pull-up.

4. CPU

4.1 ARM Cortex-M3 CPU

The CY8C52 family of devices has an ARM Cortex-M3 CPU

core. The Cortex-M3 is a low power 32-bit three-stage pipelined

Harvard architecture CPU that delivers 1.25 DMIPS/MHz. It is

intended for deeply embedded applications that require fast

interrupt handling features.

Figure 4-1. ARM Cortex-M3 Block Diagram

Interrupt Inputs

Nested

Vectored

Interrupt

Controller

(NVIC)

JTAG, SWD Debug Block

(JTAG and

SWD)

32 KB

SRAM

Bus

Matrix

Cortex M3 CPU Core

Data

Watchpoint and

Trace (DWT)

Embedded

Trace Module

(ETM)

I- Bus D-Bus

C- Bus

S-Bus

Cortex M3 Wrapper

Instrumentation

Trace Module

(ITM)

Flash Patch

and Breakpoint

(FPB)

Trace Port

Interface Unit

(TPIU)

Trace Pins:

5 for TRACEPORT or

1 for SWV mode

AHB

AHB

Bus

Matrix

Cache

256 KB

Flash

32 KB

SRAM

Bus

Matrix

AHB Spokes

AHB

AHB Bridge & Bus Matrix

PHUB

DMA

GPIO

Prog.

Digital

Prog.

Analog

Special

Functions

Peripherals

The Cortex-M3 CPU subsystem includes these features:

„ ARM Cortex-M3 CPU

„ Programmable nested vectored interrupt controller (NVIC),

tightly integrated with the CPU core

„ Full-featured debug and trace module, tightly integrated with

the CPU core

„ Up to 256 KB of flash memory, 2 KB of EEPROM, and 64 KB

of SRAM

„ Cache controller

„ Peripheral HUB (PHUB)

„ DMA controller

4.1.1 Cortex-M3 Features

The Cortex-M3 CPU features include:

„ 4-GB address space. Predefined address regions for code,

data, and peripherals. Multiple buses for efficient and

simultaneous accesses of instructions, data, and peripherals.

Document Number: 001-66236 Rev. **

Page 9 of 94

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