CY8C52(2011_03) 查看數據表（PDF） - Cypress Semiconductor
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CY8C52 Datasheet PDF : 94 Pages
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PRELIMINARY
PSoC® 5: CY8C52 Family Datasheet
1. Architectural Overview
Introducing the CY8C52 family of ultra low power, flash Programmable System-on-Chip (PSoC) devices, part of a scalable 8-bit
PSoC 3 and 32-bit PSoC 5 platform. The CY8C52 family provides configurable blocks of analog, digital, and interconnect circuitry
around a CPU subsystem. The combination of a CPU with a flexible analog subsystem, digital subsystem, routing, and I/O enables
a high level of integration in a wide variety of consumer, industrial, and medical applications.
Figure 1-1. Simplified Block Diagram
4- 25 MHz
( Optional)
32.768 KHz
( Optiona)l
System Wide
Resources
Xtal
Osc
IMO
RTC
Timer
WDT
and
Wake
ILO
Clocking System
Power Management
System
POR and
LVD
Sleep
Power
1.8 V LDO
SMP
Digital Interconnect
Analog Interconnect
Digital System
Universal Digital Block Array (24 x UDB)
8- Bit Quadrature Decoder
Timer
UDB
UDB
16- Bit
PWM
UDB
16- Bit PRS
UDB
UDB
UDB
UDB
I 2C Slave
UDB
UDB
8- Bit SPI
UDB
UDB
UART
UDB
UDB
12- Bit SPI
UDB
UDB
8- Bit
Timer
Logic
UDB
UDB
UDB
Logic
UDB
12- Bit PWM
UDB
UDB
UDB
UDB
UDB
CAN
2.0
I2C
Master/
Slave
4x
Timer
Counter
PWM
FS USB
2.0
System Bus
Memory System
EEPROM
SRAM
CPU System
8051 or
Cortex M3 CPU
Interrupt
Controller
EMIF
FLASH
Cache
Controller
PHUB
DMA
Program &
Debug
Program
Debug &
Trace
Boundary
Scan
LCD Direct
Drive
Digital
Filter
Block
4 x SC / CT Blocks
(TIA, PGA, Mixer etc)
Temperature
Sensor
CapSense
4x DAC
Analog System
ADCs
2x
SAR
ADC
1x
Del Sig
ADC
+
4x
Opamp
-
+
4x
CMP
-
USB
PHY
22 Ω
3 per
Opamp
0. 5 to5.5 V
( Optiona)l
Figure 1-1 on page 3 illustrates the major components of the
CY8C52 family. They are:
ARM Cortex-M3 CPU subsystem
Nonvolatile subsystem
Programming, debug, and test subsystem
Inputs and outputs
Clocking
Power
Digital subsystem
Analog subsystem
PSoC’s digital subsystem provides half of its unique
configurability. It connects a digital signal from any peripheral to
any pin through the digital system interconnect (DSI). It also
provides functional flexibility through an array of small, fast, low
power UDBs. PSoC Creator provides a library of pre-built and
tested standard digital peripherals (UART, SPI, LIN, PRS, CRC,
timer, counter, PWM, AND, OR, and so on) that are mapped to
the UDB array. The designer can also easily create a digital
circuit using boolean primitives by means of graphical design
entry. Each UDB contains programmable array logic
(PAL)/programmable logic device (PLD) functionality, together
with a small state machine engine to support a wide variety of
peripherals.
Document Number: 001-66236 Rev. **
Page 3 of 94
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