CYM1441-25 查看數據表（PDF） - Cypress Semiconductor
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CYM1441-25 Datasheet PDF : 6 Pages
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CYM1441
Switching Characteristics Over the Operating Range[3]
Parameter
Description
READ CYCLE
tRC
Read Cycle Time
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
tACS
CS LOW to Data Valid
tLZCS
tHZCS
CS LOW to Low Z
CS HIGH to High Z[4]
tPU
CS LOW to Power-Up
tPD
CS HIGH to Power-Down
WRITE CYCLE[5]
tWC
Write Cycle Time
tSCS
CS LOW to Write End
tAW
Address Set-Up to Write End
tHA
Address Hold from Write End
tSA
Address Set-Up to Write Start
tPWE
WE Pulse Width
tSD
Data Set-Up to Write End
tHD
Data Hold from Write End
tLZWE
tHZWE
WE HIGH to Low Z
WE LOW to High Z[4]
Shaded area contains preliminary information.
1441-20
Min. Max.
20
20
3
20
3
12
0
20
20
15
15
2
0
15
13
0
3
0
13
Switching Waveforms
1441-25
Min. Max.
25
25
3
25
3
15
0
25
25
20
20
2
0
20
15
0
3
0
15
1441-35
Min. Max.
35
35
3
35
3
25
0
35
35
30
30
2
0
25
20
0
3
0
20
1441-45
Min. Max.
45
45
3
45
3
30
0
45
45
35
35
2
2
30
20
0
3
0
25
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
[6,7]
Read Cycle No. 1
tRC
ADDRESS
DATAOUT
tAA
tOHA
PREVIOUS DATA VALID
DATA VALID
Notes:
3. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 30-pF load capacitance.
4. tHZCS and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads and Waveforms. Transition is measured ±500 mV from steady state voltage.
5. The internal write time of the memory is defined by the overlap of CS LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
6. WE is HIGH for read cycle.
7. Device is continuously selected, CS = VIL.
Document #: 38-05271 Rev. **
Page 3 of 6
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