CYRF69103(2007) 查看數據表（PDF） - Cypress Semiconductor
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CYRF69103 Datasheet PDF : 73 Pages
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CYRF69103
SPI interface. The device will enter sleep mode within 35 µs
after the last SCK positive edge at the end of this SPI trans-
action. Alternatively, the device may be configured to automat-
ically enter sleep mode after completing packet transmission
or reception. When in sleep mode, the on-chip oscillator is
stopped, but the SPI interface remains functional. The device
will wake from sleep mode automatically when the device is
commanded to enter transmit or receive mode. When
resuming from sleep mode, there is a short delay while the
oscillator restarts. The device may be configured to assert the
IRQ pin when the oscillator has stabilized.
The output voltage (VREG) of the Power Management Unit
(PMU) is configurable to several minimum values between
2.4V and 2.7V. VREG may be used to provide up to 15 mA
(average load) to external devices. It is possible to disable the
PMU, and to provide an externally regulated DC supply
voltage to the device in the range 2.4V to 3.6V. The PMU also
provides a regulated 1.8V supply to the logic.
The PMU has been designed to provide high boost efficiency
(74–85% depending on input voltage, output voltage and load)
when using a Schottky diode and power inductor, eliminating
the need for an external boost converter in many systems
where other components require a boosted voltage. However,
reasonable efficiencies (69–82% depending on input voltage,
output voltage and load) may be achieved when using
low-cost components such as SOT23 diodes and 0805
inductors.
The PMU also provides a configurable low battery detection
function which may be read over the SPI interface. One of
seven thresholds between 1.8V and 2.7V may be selected.
The interrupt pin may be configured to assert when the voltage
on the VBAT pin falls below the configured threshold. LV IRQ
is not a latched event. Battery monitoring is disabled when the
device is in sleep mode.
The following three figures show different examples of how to
use PRoC LP with and without the PMU. Figure 3. shows the
most common circuit making use of the PMU to boost battery
voltage up to 2.7v. Figure 4. is an example of the circuit used
when the supply voltage will always be above 2.7V. This could
be three 1.5v battery cells in series along with a linear
regulator, or some similar power source. Figure 5. shows an
example of using the PRoC LP with its PMU disabled and an
external boost to supply power to the device. This might be
required when the load is much greater than the 15 mA
average load that PRoC can support.
Figure 3. PMU Enabled
VBat
VCC
1 Ohm 1%
47 Ohm
10µF
6.3V
1µF
6.3V
0.047µF
0.047µF
0.047µF
0.047µF
0.047µF
0.047µF
VCC
VDD_MICRO
0.1µF
PRoC LP
VBat
100µF 10V
10 H
VCC
BAT400D
10µF6.3V
Figure 4. PMU Disabled - Linear Regulator
VCC
0.047µF
0.047µF
0.047µF
0.047µF
0.047µF
0.047µF
0.047µF
0.047µF
VCC
VDD_MICRO
0.1µF
PRoC LP
Document #: 001-07611 Rev *B
Page 7 of 73
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