CYRF69303 查看數據表（PDF） - Cypress Semiconductor

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CYRF69303

Programmable Radio-on-Chip LPstar

Cypress Semiconductor 

CYRF69303

Functional Description

PRoC LPstar devices are integrated radio and microcontroller

functions in the same package to provide a dual-role single-chip

solution.

Communication between the microcontroller and the radio is

through the radio’s SPI interface.

Functional Overview

The CYRF69303 is a complete Radio System-on-Chip device,

providing a complete RF system solution with a single device and

a few discrete components. The CYRF69303 is designed to

implement low-cost wireless systems operating in the worldwide

2.4 GHz Industrial, Scientific, and Medical (ISM) frequency band

(2.400 GHz to 2.4835 GHz).

2.4 GHz Radio Function

The SoC contains a 2.4 GHz, 1 Mbps GFSK radio transceiver,

packet data buffering, packet framer, DSSS baseband controller,

received signal strength indication (RSSI), and SPI interface for

data transfer and device configuration.

The radio supports 98 discrete 1 MHz channels (regulations may

limit the use of some of these channels in certain jurisdictions).

The baseband performs DSSS spreading/despreading, Start of

Packet (SOP), End of Packet (EOP) detection, and CRC16

generation and checking. The baseband may also be configured

to automatically transmit Acknowledge (ACK) handshake

packets whenever a valid packet is received.

When in receive mode, with packet framing enabled, the device

is always ready to receive data transmitted at any of the

supported bit rates. This enables the implementation of

mixed-rate systems in which different devices use different data

rates. This also enables the implementation of dynamic data rate

systems that use high data rates at shorter distances or in a

low-moderate interference environment or both. It changes to

lower data rates at longer distances or in high interference

environments or both.

Data Transmission Modes

The radio supports two different data transmission modes:

■ In GFSK mode, data is transmitted at 1 Mbps, without any

DSSS

■ In DSSS mode eight bits (8DR, 32 chip) are encoded in each

derived code symbol transmitted, resulting in effective 250 kbps

data rate.

32 chip Pseudo Noise (PN) codes are supported. The two data

transmission modes apply to the data after the SOP. In particular

the length, data, and CRC16 are all sent in the same mode. In

general, DSSS reduce packet error rate in any environment.

Microcontroller Function

The MCU function is an 8-bit Flash-programmable

microcontroller. The instruction set is optimized specifically for

HID and a variety of other embedded applications.

The MCU function has up to 8 Kbytes of Flash for user’s code

and up to 256 bytes of RAM for stack space and user variables.

In addition, the MCU function includes a Watchdog timer, a

vectored interrupt controller, a 16-bit Free Running Timer, and

12-bit Programmable Interrupt Timer.

The microcontroller has 15 GPIO pins grouped into multiple

ports. With the exception of the four radio function GPIOs, each

GPIO port supports high impedance inputs, configurable pull-up,

open drain output, CMOS/TTL inputs and CMOS output. Up to

two pins support programmable drive strength of up to 50 mA.

Additionally, each I/O pin can be used to generate a GPIO

interrupt to the microcontroller. Each GPIO port has its own GPIO

interrupt vector with the exception of GPIO Port 0. GPIO Port 0

has two dedicated pins that have independent interrupt vectors

(P0.3 - P0.4).

The microcontroller features an internal oscillator.

Backward Compatibility

The CYRF69303 IC is fully interoperable with the main modes of

the second generation Cypress radio SoC namely the

CYRF6936, CYRF69103 and CYRF69213.

CYRF69303 IC device may transmit data to or receive data from

a second generation device, or both.

Document Number: 001-66502 Rev. *D

Page 4 of 70

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