QL5732-33BPQ208M 查看數據表（PDF） - QuickLogic Corporation

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QL5732-33BPQ208M

33 MHz/32-bit PCI Master/Target with Embedded Programmable Logic and Dual Port SRAM

QuickLogic Corporation 

QL5732 Enhanced QuickPCI Device Data Sheet Rev. E

[9:0]

[17:0]

[1:0]

WA

RE

WD

WE

WCL K

RCLK

[9:0]

RA

[17:0]

RD

MOD E

ASYNCRD

RAM Module

Figure 4: RAM Module

QL5732 Embedded Computational Unit (ECU)

Traditional Programmable Logic architectures do not implement arithmetic functions efficiently—

these functions require high logic cell usage while achieving only moderate performance results.

The QL5732 architecture allows for functionality above and beyond that achievable using

programmable logic devices. By embedding a dynamically reconfigurable computational unit, the

QL5732 device can address various arithmetic functions efficiently—this approach offers greater

performance than traditional programmable logic implementations. The embedded block is

implemented at the transistor level as shown in Figure 5.

RESET

S1

S2

S3

CIN

SIGN1

SIGN2

A[0:7]

A[8:15]

D

C

3-4

decoder

B

A

8-bit

2-1

Multiplier

mux

16-bit

Adder

DQ

17 inc. 17-bit

COUT Register

00

01 3-1

mux

10

Q[0:16]

A[0:15]

CLK

B[0:15]

2-1

mux

Figure 5: ECU Block Diagram

The 12 QL5732 ECU blocks are placed next to the SRAM circuitry for efficient

memory/instruction fetch and addressing for DSP algorithmic implementations.

© 2003 QuickLogic Corporation

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