QL5732-33BPQ208M 查看數據表（PDF） - QuickLogic Corporation

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QL5732-33BPQ208M

33 MHz/32-bit PCI Master/Target with Embedded Programmable Logic and Dual Port SRAM

QuickLogic Corporation 

QL5732 Enhanced QuickPCI Device Data Sheet Rev. E

Configurable FIFOs

FIFOs may be created with the RAM/FIFO wizard in the QuickWorks tools. Figure 2 shows the

graphical interface used to create these FIFOs. FIFOs may be designed up to 1,024 words deep.

The 22 RAM cells available in the QL5732 allow for up to:

• 11 FIFOs at 128 words deep (36 wide)

• 5 FIFOs at 256 words deep (36 wide)

• 2 FIFOs at 512 words deep (44 wide)

• 1 FIFO at 1,024 words deep (44 wide)

Figure 2: Graphical Interface to create FIFO

PCI Interface Symbol

Figure 2 shows the graphical interface symbol numbers you have to use in your schematic design

in order to attach the local interface programmable logic design to the PCI core. If you are

designing with a top-level Verilog or VHDL file you must use a structural instantiation of this

PCI32_25µm block (Figure 3) instead of a graphical symbol.

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