QL5732-33BPQ208M 查看數據表（PDF） - QuickLogic Corporation

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QL5732-33BPQ208M

33 MHz/32-bit PCI Master/Target with Embedded Programmable Logic and Dual Port SRAM

QuickLogic Corporation 

QL5732 Enhanced QuickPCI Device Data Sheet Rev. E

PCI Master Interface

The internal signals used to interface with the PCI controller in the QL5732 are listed in Table 1

along with a description of each signal. The direction of the signal indicates if the signal is an input

provided by the local interface (I) or an output provided by the PCI controller (O).

NOTE: Signals that end with the character ‘N’ should be considered active-low (for example,

Mst_IRDYN).

Table 1: PCI Master Interface

Signal

I/O

Description

PCI_cmd[3:0]

I

mst_burst_req

I

mst_wrAd[31:0] I

mst_rdAd[31:0] I

Mst_WrData[31:0] I

Mst_BE[3:0]

I

Mst_WrData_Valid I

Mst_WrData_Rdy O

Mst_BE_Sel

I

Mst_WrBurst_Done O

Mst_Rd_Term_Sel I

Mst_One_Read

I

PCI command to be used for the master transaction This signal must remain unchanged

throughout the period when Mst_Burst_Req is active. PCI commands considered as Reads include

Interrupt Acknowledge, I/O Read, Memory Read, Configuration Read, Memory Read Multiple,

and Memory Read Line. PCI commands considered as Writes include Special Cycle, I/O Write,

Memory Write, Configuration Write, Memory Write, and Invalidate.Users should make sure that

only valid PCI commands are supplied.

Request use of the PCI bus When it is active, the core requests the PCI bus and then generates

a Master transaction. This signal should be held active until all requested data is transferred on the

PCI bus and deactivated in the 2nd clock cycle following the last data transfer on PCI (to avoid

being considered as requesting a new transaction).

Address for master DMA writes This address must be treated as valid from the beginning of a

DMA Write until the DMA Write operation is complete. It should be incremented by four bytes

each time data is transferred on the PCI bus.

Address for master DMA reads This address must be treated as valid from the beginning of a

DMA read until the DMA Read operation is complete. It should be incremented by four bytes each

time data is transferred on the PCI bus.

Data for master DMA Writes (to PCI bus)

Byte enables for master DMA Reads and writes Active-low.

Data and byte enable valid on Mst_WrData[31:0] (for master Write only) and

Mst_BE[3:0] (for both master Read and Write)

Data receive acknowledge for Mst_WrData[31:0] (for master Write only) and

Mst_BE[3:0] (for both) This serves as the PUSH control for the internal FIFO and the POP

control for the external FIFO (in FPGA region) which provides data and byte enables to the PCI32

core.

Byte enable select for master transactions When low, Mst_BE[3:0] should remain constant

throughout the entire transfer (when Mst_Burst_Req is active) and it is used for every data phase of

the master transaction. When high, Mst_BE[3:0] pushed into internal FIFO (along with data in case

of master Write) is used. Should be held constant throughout the transaction.

Master Write transaction is completed Active for only one clock cycle.

Master Read termination mode select when Mst_BE_Sel is high When both Mst_BE_Sel

and Mst_Rd_Term_Sel are high, Master Read termination happens when the internal FIFO is

empty, and Mst_Two_Reads and Mst_One_Read are ignored. When either signal is low,

Mst_Two_Reads and Mst_One_Read are used to signal the end of Master Read. Should be held

constant throughout the transaction.

Signals to the PCI32 core that only one data transfer remains to be read in the burst Read.

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