GS8170DD36C-250(2005) 查看數據表（PDF） - Giga Semiconductor

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GS8170DD36C-250
(Rev.:2005)

18Mb Σ1x2Lp CMOS I/O Double Data Rate SigmaRAM™

Giga Semiconductor 

GS8170DD36C-333/300/250/200

SigmaRAM DDR Bank Switch with E1 Deselect

Read

No Op

Read

Read

Read

CK

Address

A

XX

C

D

E

F

ADV

/E1

/E2 Bank 1

E2 Bank 2

DQ

Bank 1

CQ

Bank 1

QA0

QA1

CQ1 + CQ2

CQ

Bank 2

DQ

Bank 2

QC0

QC1

QD0

QD1

Note: E1\ does not deselect the Echo Clock Outputs. Echo Clock outputs are synchronously deselected by E2 or E3 being sampled false.

CMOS Output Driver Impedance Control

CMOS I/O SigmaRAMs are supplied with selectable (high or low) impedance output drivers. The ZQ pin allows selection between

SRAM nominal drive strength (ZQ low) for multi-drop bus applications and low drive strength (ZQ high) point-to-point

applications.

Rev: 2.03 1/2005

11/29

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

© 2002, GSI Technology, Inc.

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