GS8170DD36C-250(2005) 查看數據表（PDF） - Giga Semiconductor

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GS8170DD36C-250
(Rev.:2005)

18Mb Σ1x2Lp CMOS I/O Double Data Rate SigmaRAM™

Giga Semiconductor 

GS8170DD36C-333/300/250/200

Read Operations

Double Data Rate Read

In applications where a data rate markedly faster than the RAM’s latency is desired, the Double Data Rate protocol doubles the

data transfer rate (read or write bandwidth) achieved in Pipeline mode while keeping the RAM’s clock frequency constant. In

Double Data Rate mode, the RAM multiplexes the results of a read out of the RAM on half the usual number of data pins. The

output register/mux behaves just as if it were in Pipeline mode for the first transfer, but then makes a second transfer in response to

the next falling edge of clock as well. SigmaRAM DDR RAMs burst in linear order only.

Double Data Rate Pipelined Read

Read

Deselect

Read

Read

Read

CK

Address

A

XX

C

D

E

F

ADV

/E1

/W

QA0

QA1

QC0

QC1

QD0

QD1

DQ

CQ

Key

Hi-Z

Access

Write Operations

Write operation occurs when the following conditions are satisfied at the rising edge of clock: All three chip enables (E1, E2, and

E3) are active, the write enable input signal (W) is asserted low, and ADV is asserted low.

Double Data Rate Write

A Double Data Rate Write is a specialized form of Late Write. In Double Data Rate mode, the RAM will capture Data In on both

rising and falling edges of the RAM clock, CK, beginning with the rising edge of clock that follows the capture of the write address

and command.

Rev: 2.03 1/2005

4/29

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

© 2002, GSI Technology, Inc.

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