GS8170DD36C-333I 查看數據表（PDF） - Giga Semiconductor

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GS8170DD36C-333I

18Mb Σ1x2Lp Double Data Rate SigmaRAM™ SRAM

Giga Semiconductor 

GS820H32AT/Q-150/138/133/117/100/66

Simplified State Diagram with G

X

Deselect

W

R

W

R

X

First Write R

CW

CR

W

First Read

X

CW

CR

W

X

R

Burst Write

CR

CW

R

W Burst Read X

CW

CR

Notes:

1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G.

2. Use of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from Read cycles to Write cycles without passing

through a Deselect cycle. Dummy Read cycles increment the address counter just like normal Read cycles.

3. Transitions shown in grey tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet

Data Input Set Up Time.

Rev: 1.04 3/2000

8/23

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

© 2000, Giga Semiconductor, Inc.

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