DM74LS299 查看數據表（PDF） - Fairchild Semiconductor

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DM74LS299

8-Input Universal Shift/Storage Register with Common Parallel I/O Pins

Fairchild Semiconductor 

Functional Description

The DM74LS299 contains eight edge-triggered D-type flip-

flops and the interstage logic necessary to perform syn-

chronous shift left, shift right, parallel load and hold opera-

tions. The type of operation is determined by the S0 and

S1, as shown in the Mode Select Table. All flip-flop outputs

are brought out through 3-STATE buffers to separate I/O

pins that also serve as data inputs in the parallel load

mode. Q0 and Q7 are also brought out on other pins for

expansion in serial shifting of longer words.

A LOW signal on MR overrides the Select and CP inputs

and resets the flip-flops. All other state changes are initi-

ated by the rising edge of the clock. Inputs can change

when the clock is in either state provided only that the rec-

ommended setup and hold times, relative to the rising edge

of CP, are observed.

A HIGH signal on either OE1 or OE2 disables the 3-STATE

buffers and puts the I/O pins in the high impedance state.

In this condition the shift, hold, load and reset operations

can still occur. The 3-STATE buffers are also disabled by

HIGH signals on both S0 and S1 in preparation for a paral-

lel load operation.

Logic Diagram

Mode Select Table

Inputs

MR S1 S0 CP

Response

L

H

H

H

X

H

L

H

X

H

H

L

X Asynchronous Reset; Q0–Q7 = LOW

 Parallel Load; I/On→Qn

 Shift Right; DS0→Q0, Q0→Q1, etc.

 Shift Left; DS7→Q7, Q7→Q6, etc.

H L L X Hold

H = HIGH Voltage Level

L = LOW Voltage Level

X = Immaterial

= LOW-to-HIGH Clock (CP) Transition

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