DM74S112 查看數據表（PDF） - Fairchild Semiconductor
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DM74S112
Fairchild Semiconductor
DM74S112 Datasheet PDF : 4 Pages
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Electrical Characteristics
over recommended operating free air temperature (unless otherwise noted)
Symbol
Parameter
Conditions
Typ
Min
Max
(Note 6)
VI
Input Clamp Voltage
VCC = Min, II = − 18 mA
VOH
HIGH Level
VCC = Min, IOH = Max
Output Voltage
VIL = Max, VIH = Min
VOL
LOW Level
VCC = Min, IOL = Max
Output Voltage
VIH = Min, VIL = Max
II
Input Current @ Max Input Voltage VCC = Max, VI = 5.5V
IIH
HIGH Level
VCC = Max
J, K
Input Current
VI = 2.7V
Clear
Preset
−1.2
2.7
3.4
0.5
1
50
100
100
Clock
100
IIL
LOW Level
VCC = Max
J, K
−1.6
Input Current
VI = 0.5V
Clear
−7
(Note 7)
Preset
−7
Clock
−4
IOS
Short Circuit Output Current
ICC
Supply Current
Note 6: All typicals are at VCC = 5V, TA = 25°C.
VCC = Max (Note 8)
VCC = Max (Note 9)
−40
−100
30
50
Note 7: Clear is tested with preset HIGH and preset is tested with clear HIGH.
Note 8: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note 9: With all outputs OPEN, ICC is measured with the Q and Q outputs HIGH in turn. At the time of measurement, the clock input is grounded.
Units
V
V
V
mA
µA
mA
mA
mA
Switching Characteristics
at VCC = 5V and TA = 25°C
Symbol
Parameter
fMAX
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
Maximum Clock Frequency
Propagation Delay Time
LOW-to-HIGH Level Output
Propagation Delay Time
HIGH-to-LOW Level Output
Propagation Delay Time
LOW-to-HIGH Level Output
Propagation Delay Time
HIGH-to-LOW Level Output
Propagation Delay Time
LOW-to-HIGH Level Output
Propagation Delay Time
HIGH-to-LOW Level Output
From (Input)
To (Output)
Preset to Q
Preset to Q
Clear to Q
Clear to Q
Clock to Q or Q
Clock to Q or Q
RL = 280Ω
CL = 15 pF
CL = 50 pF
Min
Max
Min
Max
80
60
7
9
7
12
7
9
7
12
7
9
7
12
Units
MHz
ns
ns
ns
ns
ns
ns
3
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