DM74S161 查看數據表（PDF） - Fairchild Semiconductor
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DM74S161 Datasheet PDF : 7 Pages
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Electrical Characteristics
over recommended operating free air temperature (unless otherwise noted)
Symbol
Parameter
Conditions
Min
VI
Input Clamp Voltage
VCC = Min, II = −18 mA
VOH
HIGH Level
VCC = Min, IOH = Max
2.7
Output Voltage
VIL = Max, VIH = Min
VOL
LOW Level
VCC = Min, IOL = Max
Output Voltage
VIH = Min, VIL = Max
II
Input Current @ Max Input Voltage VCC = Max, VI = 5.5V
IIH
LOW Level
VCC = Max
CLK, Data
Input Current
VI = 2.7V
Others
−10
IIL
LOW Level
VCC = Max
Enable T
Input Current
VI = 0.5V
Others
IOS
Short Circuit Output Current
VCC = Max (Note 7)
−40
ICC
Supply Current
VCC = Max
Note 6: All typicals are at VCC = 5V, TA = 25°C.
Note 7: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Typ
(Note 6)
3.4
95
Max
−1.2
0.5
1
50
−200
−4
−2
−100
160
Switching Characteristics
at VCC = 5V and TA = 25°C
RL = 280Ω
Symbol
Parameter
From (Input)
CL = 15 pF
CL = 50 pF
To (Output)
Min
Max
Min
Max
fMAX
tPLH
Maximum Clock Frequency
Propagation Delay Time
LOW-to-HIGH Level Output
40
35
Clock to Ripple Carry
25
25
tPHL
Propagation Delay Time
Clock to Ripple Carry
25
28
HIGH-to-LOW Level Output
tPLH
Propagation Delay Time
LOW-to-HIGH Level Output
Clock to Any Q
15
15
tPHL
Propagation Delay Time
HIGH-to-LOW Level Output
Clock to Any Q
15
18
tPLH
Propagation Delay Time
Enable T to Ripple Carry
15
18
LOW-to-HIGH Level Output
tPHL
Propagation Delay Time
Enable T to Ripple Carry
15
18
HIGH-to-LOW Level Output
tPHL
Propagation Delay Time
Clear to Any Q
HIGH-to-LOW Level Output (Note 8)
20
24
Note 8: Propagation delay for clearing is measured from clear input for the DM74S161 and from the clock input transition for the DM74S163.
Units
V
V
V
mA
µA
mA
mA
mA
Units
MHz
ns
ns
ns
ns
ns
ns
ns
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