DM9000 查看數據表（PDF） - Davicom Semiconductor, Inc.
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DM9000 Datasheet PDF : 53 Pages
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DM9000
ISA to Ethernet MAC Controller with Integrated 10/100 PHY
When it is pulled high, the LED mode is mode 1; Otherwise it is mode 0
Note: The pins EECS,EECK and EEDO are all have a pulled down resistor about 60k ohm internally
5.4 Clock Interface
21
X2_25M
22
X1_25M
59
CLK20MO
O Crystal 25MHz Out
I Crystal 25MHz In
O 20Mhz Clock Output
It is used as the clock signal for the external MII device’s clock is 20MHz
This pin has a pulled down resistor about 60k ohm internally.
5.5 LED Interface
60
SPEED100#
61
DUP#
62
LINK&ACT#
O Speed LED
Its low output indicates that the internal PHY is operated in 100M/S, or it
is floating for the 10M mode of the internal PHY
O Full-duplex LED
In LED mode 1, Its low output indicates that the internal PHY is operated
in full-duplex mode, or it is floating for the half-duplex mode of the internal
PHY
In LED mode 0, Its low output indicates that the internal PHY is operated
in 10M mode, or it is floating for the 100M mode of the internal PHY
O Link LED
In LED mode 1, it is the combined LED of link and carrier sense signal of
the internal PHY
In LED mode 0, it is the LED of the carrier sense signal of the internal
PHY only
5.6 10/100 PHY
25
BGGND
26
BGRES
27
AVDD
28
AVDD
29
RXI+
30
RXI-
31
AGND
32
AGND
33
TXO+
34
TXO-
35
AVDD
P Bandgap Ground
I/O Bandgap Pin
P Bandgap and Guard Ring Power
P RX Power
I TP RX Input
I TP RX Input
P RX Ground
P TX Ground
O TP TX Output
O TP TX Output
P TX Power
5.7 Miscellaneous
16,17,18, TEST1~TEST4
19
48
TEST5
I Operation Mode
Test 1, 2, 3, 4 = (1, 1, 0, 0) in normal application
I It must be ground.
Final
9
Version: DM9000-DS-F03
April 23, 2009
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