QL4036-0PF144C 查看數據表（PDF） - QuickLogic Corporation

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QL4036-0PF144C

36,000 usable PLD gate QuickRAM ESP combining performance, density and embedded RAM.

QuickLogic Corporation 

QL4036 - QuickRAMTM

AC CHARACTERISTICS at VCC = 3.3V, TA = 25°C (K = 1.00)

(To calculate delays, multiply the appropriate K factor in the "Operating Range" section by the following numbers.)

Logic Cells

Symbol

Parameter

tPD

tSU

tH

tCLK

tCWHI

tCWLO

tSET

tRESET

tSW

tRW

Combinatorial Delay [6]

Setup Time [6]

Hold Time

Clock to Q Delay

Clock High Time

Clock Low Time

Set Delay

Reset Delay

Set Width

Reset Width

Propagation Delays (ns)

Fanout [5]

1

2

3

4

8

1.4

1.7

1.9

2.2

3.2

1.7

1.7

1.7

1.7

1.7

0.0

0.0

0.0

0.0

0.0

0.7

1.0

1.2

1.5

2.5

1.2

1.2

1.2

1.2

1.2

1.2

1.2

1.2

1.2

1.2

1.0

1.3

1.5

1.8

2.8

0.8

1.1

1.3

1.6

2.6

1.9

1.9

1.9

1.9

1.9

1.8

1.8

1.8

1.8

1.8

RAM Cell Synchronous Write Timing

Symbol

Parameter

1

TSWA

WA Setup Time to WCLK

1.0

THWA

WA Hold Time to WCLK

0.0

TSWD

WD Setup Time to WCLK

1.0

THWD

WD Hold Time to WCLK

0.0

TSWE

WE Setup Time to WCLK

1.0

THWE

WE Hold Time to WCLK

0.0

TWCRD

WCLK to RD (WA=RA) [5]

5.0

Propagation Delays (ns)

Fanout

2

3

4

8

1.0

1.0

1.0

1.0

0.0

0.0

0.0

0.0

1.0

1.0

1.0

1.0

0.0

0.0

0.0

0.0

1.0

1.0

1.0

1.0

0.0

0.0

0.0

0.0

5.3

5.6

5.9

7.1

Notes:

[5]Stated timing for worst case Propagation Delay over process variation at VCC=3.3V and TA=25°C. Multiply by

the appropriate Delay Factor, K, for speed grade, voltage and temperature settings as specified in the Operating

Range.

[6]These limits are derived from a representative selection of the slowest paths through the QuickRAM logic cell

including typical net delays. Worst case delay values for specific paths should be determined from timing anal-

ysis of your particular design.

6-39

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