DP80C51 查看數據表（PDF） - Digital Core Design
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DP80C51 Datasheet PDF : 10 Pages
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SYMBOL
ea
prgromdatai(7:0)
prgramdatai(7:0)
port0(7:0)
port1(7:0)
port2(7:0)
port3(7:0)
ale
psen
pswr
prgaddr(15:0)
prgdatao(7:0)
prgramwr
ramdatai(7:0)
ramaddr(7:0)
ramdatao(7:0)
ramwe
ramoe
sfrdatai(7:0)
tdi
tck
tms
reset
clk
sfraddr(6:0)
sfrdatao(7:0)
sfroe
sfrwe
stop
pmm
tdo
rtck
coderun
debugacs
rsto
PINS DESCRIPTION
PIN
TYPE
DESCRIPTION
clk
input Global clock
reset
input Global reset input
port0[7:0]
bidir I/O Port 0, multifunctional
Data/LSB address of external memory
port1[7:0]
bidir I/O Port 1
port2[7:0]
bidir I/O Port 2, multifunctional
MSB address of external memory
port3[0]
bidir I/O Port 3.0
Serial receiver input/output port
port3[1]
bidir I/O Port 3.1
Serial transmitter output port
port3[2]
bidir I/O Port 3.2, multifunctional
Interrupt 0 input/timer 0 gate
port3[3]
bidir I/O Port 3.3, multifunctional
Interrupt 1 input/timer 1 gate
port3[4]
bidir I/O Port 3.4, multifunctional
Timer 0 external clock line
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PIN
TYPE
DESCRIPTION
port3[5]
bidir I/O Port 3.5, multifunctional
Timer 1 external clock line
port3[6]
bidir I/O Port 3.6
External Data Memory write
port3[7]
bidir I/O Port 3.7
External Data Memory read
ea
input Enable all external program memory
prgramdatai[7:0] input Data bus from int. RAM prog. memory
prgromdatai[7:0] input Data bus from int. ROM prog. memory
ramdatai[7:0]
input Data bus from internal data memory
sfrdatai[7:0]
input Data bus from user SFR’s
tdi
input DoCD™ TAP data input
tck
input DoCD™ TAP clock input
tms
input DoCD™ TAP mode select input
rsto
output Reset output
prgaddr[15:0] output Internal program memory address bus
prgdatao[7:0] output Data bus for internal program memory
prgramwr
output Internal program memory write
ale
output Address Latch Enable
psen
output Program Store (memory) read Enable
pswr
output Program Store (memory) Write
ramaddr[7:0]
output Internal Data Memory address bus
ramdatao[7:0] output Data bus for internal data memory
ramoe
output Internal data memory output enable
ramwe
output Internal data memory write enable
sfraddr[6:0]
output Address bus for user SFR’s
sfrdatao[7:0]
output Data bus for user SFR’s
sfroe
output User SFR’s read enable
sfrwe
output User SFR’s write enable
tdo
output DoCD™ TAP data output
rtck
output DoCD™ return clock line
debugacs
output DoCD™ accessing data
coderun
output CPU is executing an instruction
pmm
output Power management mode indicator
stop
output Stop mode indicator
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