DP805X 查看數據表（PDF） - Digital Core Design

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DP805X

Pipelined High Performance Microcontroller

Digital Core Design 

DP805x Instructions set details

2.2.4. DATA TRANSFERS

-9-

Mnemonic

Description

MOV A,Rn

Move register to accumulator

MOV A,direct

Move direct byte to accumulator

MOV A,@Ri

Move indirect RAM to accumulator

MOV A,#data

Move immediate data to accumulator

MOV Rn,A

Move accumulator to register

MOV Rn,direct

Move direct byte to register

MOV Rn,#data

Move immediate data to register

MOV direct,A

Move accumulator to direct byte

MOV direct,Rn

Move register to direct byte

MOV direct1,direct2 Move direct byte to direct byte

MOV direct,@Ri

Move indirect RAM to direct byte

MOV direct,#data Move immediate data to direct byte

MOV @Ri,A

Move accumulator to indirect RAM

MOV @Ri,direct

Move direct byte to indirect RAM

MOV @Ri,#data

Move immediate data to indirect RAM

MOV DPTR,#data16 Load data pointer with a 16-bit constant

MOVC A,@A+DPTR Move code byte relative to DPTR to accumulator

MOVC A,@A+PC Move code byte relative to PC to accumulator

MOVX A,@Ri

Move external RAM (8-bit address) to A

MOVX A,@DPTR Move external RAM (16-bit address) to A

CODE inside ROM/RAM

MOVX @Ri,A

Move A to external destination XRAM data

RAM (8-bit address) all other cases

Code Bytes Cycles

0xE8-0xEF 1

1

0xE5

2

2

0xE6-0xE7 1

2

0x74

2

2

0xF8-0xFF 1

1

0xA8-0xAF 2

3

0x78-0x7F 2

2

0xF5

2

2

0x88-8F

2

2

85

3

3

86-87

2

3

75

3

3

F6-F7

1

2

A6-A7

2

3

76-77

2

2

90

3

3

93

1

5

83

1

4

E2-E3

1

3*

E0

1

2*

4*

F2-F3

1

5*

MOVX @DPTR,A

CODE inside ROM/RAM

Move A to external destination XRAM data

RAM (16-bit address) all other cases

F0

3*

1

4*

PUSH direct

POP direct

XCH A,Rn

XCH A,direct

XCH A,@Ri

XCHD A,@Ri

Push direct byte onto stack

C0

2

3

Pop direct byte from stack

D0

2

2

Exchange register with accumulator

C8-CF

1

2

Exchange direct byte with accumulator

C5

2

3

Exchange indirect RAM with accumulator

C6-C7

1

3

Exchange low-order nibble indirect RAM with A

D6-D7

1

3

Table 6. Data transfer

* MOVX cycles depends on STRETCH register. Table shows values with STRETCH=0.

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