DS1554 查看數據表（PDF） - Maxim Integrated
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DS1554 Datasheet PDF : 18 Pages
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DS1554 256k, Nonvolatile, Y2K-Compliant Timekeeping RAM
Table 2. Register Map
ADDRESS
B7
7FFFh
7FFEh
X
7FFDh
X
DATA
B6
B5
B4
B3
10 Year
X
X
10
Month
X
10 Date
B2
B1 B0
Year
Month
Date
7FFCh
X
FT
X
X
X
Day
7FFBh
X
X
10 Hour
Hour
7FFAh
7FF9h
7FF8h
7FF7h
X
OSC
W
WDS
10 Minutes
10 Seconds
R
10 Century
BMB4 BMB3 BMB2
Minutes
Seconds
Century
BMB1 BMB0 RB1 RB0
7FF6h
AE
Y
ABE
Y
Y
Y
YY
7FF5h AM4 Y
10 Date
Date
7FF4h AM3 Y
10 Hours
Hours
7FF3h
7FF2h
7FF1h
AM2
AM1
Y
10 Minutes
10 Seconds
Y
Y
Y
Minutes
Seconds
Y
Y
YY
7FF0h
WF AF
0
BLF
0
0
00
FUNCTION/RANGE
Year
Month
Date
Day
Hour
Minutes
Seconds
Control
Watchdog
Interrupts
Alarm Date
Alarm Hours
Alarm Minutes
Alarm Seconds
Unused
Flags
00-99
01-12
01-31
01-07
00-23
00-59
00-59
00-39
—
—
01-31
00-23
00-59
00-59
—
—
X = Unused, Read/Writeable under Write and Read Bit Control
Y = Unused, Read/Writeable without Write and Read Bit Control
FT = Frequency Test Bit
OSC = Oscillator Start/Stop Bit
W = Write Bit
R = Read Bit
WDS = Watchdog Steering Bit
BMB0 to BMB4 = Watchdog Multiplier Bits
AE = Alarm Flag Enable
ABE = Alarm in Battery-Backup Mode Enable
AM1-AM4 = Alarm Mask Bits
WF = Watchdog Flag
AF = Alarm Flag
0 = 0 (Read Only)
BLF = Battery Low Flag
RB0 to RB1 = Watchdog Resolution Bits
CLOCK OSCILLATOR CONTROL
The Clock oscillator may be stopped at any time. To increase the shelf life of the backup lithium battery
source, the oscillator can be turned off to minimize current drain from the battery. The OSC bit is the
MSB of the Seconds Register (B7 of 7FF9h). Setting it to a 1 stops the oscillator, setting to a 0 starts the
oscillator. The DS1554 is shipped from Maxim with the clock oscillator turned off, OSC bit set to a 1.
READING THE CLOCK
When reading the RTC data, it is recommended to halt updates to the external set of double-buffered RTC
Registers. This puts the external registers into a static state allowing data to be read without register
values changing during the read process. Normal updates to the internal registers continue while in this
state. External updates are halted when a 1 is written into the read bit, B6 of the Control Register (7FF8h).
As long as a 1 remains in the Control Register read bit, updating is halted. After a halt is issued, the
registers reflect the RTC count (day, date, and time) that was current at the moment the halt command
was issued. Normal updates to the external set of registers will resume within 1 second after the read bit is
set to a 0 for a minimum of 500 s. The read bit must be a zero for a minimum of 500 s to ensure the
external registers will be updated.
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