DS1557P 查看數據表（PDF） - Maxim Integrated

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DS1557P

4Meg, Nonvolatile, Y2K-Compliant Timekeeping RAM

Maxim Integrated 

Figure 1. Block Diagram

DS1557 4Meg, Nonvolatile, Y2K-Compliant Timekeeping RAM

Maxim

DS1557

Table 1. Operating Modes

VCC

CE OE

VIH X

VCC > VPF

VIL X

VIL VIL

VIL VIH

VSO < VCC <VPF X

X

VCC < VSO <VPF X

X

WE DQ0–DQ7

X HIGH-Z

VIL

DIN

VIH

DOUT

VIH HIGH-Z

X HIGH-Z

X HIGH-Z

MODE

Deselect

Write

Read

Read

Deselect

Data Retention

POWER

Standby

Active

Active

Active

CMOS Standby

Battery Current

DATA READ MODE

The DS1557 is in the read mode whenever CE (chip enable) is low and WE (write enable) is high. The

device architecture allows ripple-through access to any valid address location. Valid data will be available

at the DQ pins within tAA after the last address input is stable, providing that CE and OE access times are

satisfied. If CE or OE access times are not met, valid data will be available at the latter of chip enable

access (tCEA) or at output enable access time (tOEA). The state of the data input/output pins (DQ) is

controlled by CE and OE . If the outputs are activated before tAA, the data lines are driven to an

intermediate state until tAA. If the address inputs are changed while CE and OE remain valid, output data

will remain valid for output data hold time (tOH) but will then go indeterminate until the next address

access.

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