DS1646 查看數據表（PDF） - Dallas Semiconductor -> Maxim Integrated

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DS1646

Nonvolatile Timekeeping RAM

Dallas Semiconductor -> Maxim Integrated 

DS1646/DS1646P

DS1646 REGISTER MAP – BANK1 Table 2

DATA

ADDRESS

B7

B6

B5

B4

B3

B2

B1

B0

1FFFF

–

–

–

–

–

–

–

–

FUNCTION

YEAR 00–99

1FFFE

X

X

X

–

–

–

–

–

MONTH 01–12

1FFFD

X

X

–

–

–

–

–

–

DATE 01–31

1FFFC

X

FT

X

X

X

–

–

–

DAY

01–07

1FFFB

X

X

–

–

–

–

–

–

HOUR 00–23

1FFFA

X

–

–

–

–

–

–

–

MINUTES 00–59

1FFF9

OSC

–

–

–

–

–

–

– SECONDS 00–59

1FFF8

W

R

X

X

X

X

X

X CONTROL A

OSC = STOP BIT

W = WRITE BIT

R = READ BIT

X = UNUSED

FT = FREQUENCY TEST

NOTE:

All indicated “X” bits are not dedicated to any particular function and can be used as normal RAM bits.

RETRIEVING DATA FROM RAM OR CLOCK

The DS1646 is in the read mode whenever WE (write

enable) is high, CE (chip enable) is low. The device ar-

chitecture allows ripple–through access to any of the

address locations in the NVSRAM. Valid data will be

available at the DQ pins within tAA after the last address

input is stable, providing that the CE and OE access

times and states are satisfied. If CE or OE access times

are not met, valid data will be available at the latter of

chip enable access (tCEA) or at output enable access

time (tOEA). The state of the data input/output pins (DQ)

is controlled by CE and OE. If the outputs are activated

before tAA, the data lines are driven to an intermediate

state until tAA. If the address inputs are changed while

CE and OE remain valid, output data will remain valid for

output data hold time (tOH) but will then go indeterminate

until the next address access.

WRITING DATA TO RAM OR CLOCK

The DS1646 is in the write mode whenever WE and CE

are in their active state. The start of a write is referenced

to the latter occurring high to low transition of WE and

CE. The addresses must be held valid throughout the

cycle. CE or WE must return inactive for a minimum of

tWR prior to the initiation of another read or write cycle.

Data in must be valid tDS prior to the end of write and re-

main valid for tDH afterward. In a typical application, the

OE signal will be high during a write cycle. However,

OE can be active provided that care is taken with the

data bus to avoid bus contention. If OE is low prior to

WE transitioning low the data bus can become active

with read data defined by the address inputs. A low tran-

sition on WE will then disable the outputs tWEZ after WE

goes active.

DATA RETENTION MODE

When VCC is within nominal limits (VCC > 4.5 volts) the

DS1646 can be accessed as described above with read

or write cycles. However, when VCC is below the pow-

er–fail point VPF (point at which write protection occurs)

the internal clock registers and RAM are blocked from

access. This is accomplished internally by inhibiting ac-

cess via the CE signal. At this time the power–fail output

signal (PFO) will be driven active low and will remain

active until VCC returns to nominal levels. When VCC

falls below the level of the internal battery supply, power

input is switched from the VCC pin to the internal battery

and clock activity, RAM, and clock data are maintained

from the battery until VCC is returned to nominal level.

031698 4/12

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