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DS1831BS 查看數據表(PDF) - Maxim Integrated

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DS1831BS
MaximIC
Maxim Integrated MaximIC
DS1831BS Datasheet PDF : 14 Pages
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DS1831/A/B
OUTPUT VALID CONDITIONS
The DS1831 can maintain valid outputs as long as one input remains above 1.0V. Accurate voltage
monitoring additionally requires that either the 3.3V IN or 5V IN input be above 1.5V. If this condition is
not met and at least one of the supply inputs are at or above 1.0V all outputs are maintained in the active
condition. The DS1831 requires pull-up resistors on the outputs to maintain a valid output. The value of
the pull up resistor is not critical in most cases but must be set low enough to pull the output to a high
state. A common pull-up resistor value used is 10kW (see Figure 7).
APPLICATION DIAGRAM—OPEN DRAIN OUTPUTS Figure 7
5V Supply
3.3V Supply
10 KW
IN5V
RST5V
TOL5V
TD5V
PBRST5V
1
16
2 DS1831 15
3
14
4
13
5
12
IN3.3v
RST3.3V
TOL3.3V
TD3.3V
PBRST3.3V
GND
10 kW
NOTE: If outputs are at different voltages the outputs can not be connected to form a wired AND.
OPERATION—NON-MASKABLE INTERRUPT
The DS1831 has two referenced comparator (DS1831A has only one referenced comparator) that can be
used to monitor upstream voltages or other system specific voltages. Each comparator is referenced to the
1.25V internal band gap reference and controls an open-drain output. When a voltage being monitored
decays to the voltage sense point, the DS1831 pulses the NMI output to the active state for a minimum
10µs. The comparator detection circuitry also has built-in hysteresis of 100µV. The supply must be below
the voltage sense point for approximately 2µs before a low NMI will be generated. In this way, power
supply noise is minimized in the monitoring function, reducing false interrupts. See Figure 8 for the non-
maskable timing diagram.
Versatile trip voltages can be configured by the use of an external resistor divider to divide the voltage at
a sense point to the 1.25V trip levels of the referenced comparators. See Figure 9 for an example circuit
diagram and sample equations. The equations demonstrate a design process to determine the resistor
values to use.
Connecting one or both NMI outputs to one of the reset specific PBRST s allows the non-maskable
interrupt to generate an automatic reset for the reset time period when an out-of-tolerance condition
occurs in a monitored supply. An example is shown in Figure 9.
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