DS1855 查看數據表（PDF） - Dallas Semiconductor -> Maxim Integrated

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DS1855

Dual Nonvolatile Digital Potentiometer and Secure Memory

Dallas Semiconductor -> Maxim Integrated 

DS1855 BLOCK DIAGRAM Figure 1

DS1855

VCC

GND

SDA

SCL

WP

A0

A1

A2

2-WIRE

INTERFACE

248 BYTES

EEPROM

MEMORY

1 BYTE WIPER

CONTROL SETTING

POT 0

DATA

1 BYTE WIPER

SETTING

POT 1

CONFIGURATION

BYTE

LOCK BYTE

LOCK BYTE

RESERVED

POTENTIOMETER 0

H0

100-

Position

W0

Pot

L0

POTENTIOMETER 1

256-

H1

Position

Pot

W1

L1

Up to eight DS1855s can be installed on a single 2-wire bus. Access to an individual device is achieved

by using a device address that is determined by the logic levels of address pins A0 through A2.

Additionally, the DS1855 will operate from 3V or 5V supplies. Three package options are available: 14-

pin TSSOP, 16-ball STPBGA, and flip-chip package.

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