DS1868-010 查看數據表（PDF） - Dallas Semiconductor -> Maxim Integrated
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DS1868-010 Datasheet PDF : 14 Pages
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CAPACITANCE
PARAMETER
Input Capacitance
Output Capacitance
SYMBOL
CIN
COUT
MIN
TYP
MAX
5
7
DS1868
(tA=25°C)
UNITS NOTES
pF
3, 6
pF
3, 6
AC ELECTRICAL CHARACTERISTICS
(-40°C to +85°C; VCC=5.0V ± 10%)
PARAMETER
SYMBOL MIN TYP MAX UNITS NOTES
CLK Frequency
fCLK
DC
10 MHz
10
Width of CLK Pulse
tCH
50
ns
10
Data Setup Time
tDC
30
ns
10
Data Hold Time
tCDH
10
ns
10
Propagation Delay Time Low to High Level
tPLH
Clock to Output
50
ns
10, 13
Propagation Delay Time High to Low Level
tPLH
50
ns
10, 13
RST High to Clock Input High
tCC
50
ns
10
RST Low from Clock Input High
tHLT
50
ns
10
RST Inactive
tRLT
125
ns
10
Clock Low to Data Valid on a Read
tCDD
30
ns
10
CLK Rise Time, CLK Fall Time
tCR
50
ns
10
NOTES:
1. All voltages are referenced to ground.
2. Resistor inputs cannot exceed VB - 0.5V in the negative direction.
3. Capacitance values apply at 25°C.
4. Absolute linearity is used to determine wiper voltage versus expected voltage as determined by wiper
position. Device test limits ±1.6 LSB.
5. Relative linearity is used to determine the change in voltage between successive tap positions. Device
test limits ±0.5 LSB.
6. Typical values are for tA = 25°C and nominal supply voltage.
7. -3 dB cutoff frequency characteristics for the DS1868 depend on potentiometer total resistance:
DS1868-010; 1 MHz, DS1868-050; 200 kHz; and DS1868-100; 80 kHz.
8. Cout is active regardless of the state of RST .
9. VREF = 1.5 volts.
10. See Figure 9(a), (b), and (c).
11. Noise < -120 dB/ Hz . Reference 1 volt (thermal).
12. Supply current is dependent on clock rate (see Figure 11).
13. See Figure 10.
14. Standby currents apply when RST , LLIC, DQ are in the low-state.
15. When biasing the substrate minimum VB = -3.0V ± 10% and maximum VCC = 3.0V ± 10%.
16. Valid at 25°C only.
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