DS1863 查看數據表（PDF） - Maxim Integrated

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DS1863

Burst-Mode PON Controller With Integrated Monitoring

Maxim Integrated 

Burst-Mode PON Controller

With Integrated Monitoring

Modulation Control

The MOD voltage is controlled using an internal tem-

perature indexed Lookup Table.

The MOD output is an 8-bit scaleable voltage output that

interfaces with the MAX3643’s VMSET input. An external

resistor to ground from the MAX3643’s MODSET pin sets

the maximum current the voltage at VMSET input can

produce for a given output range. This resistor value

should be chosen to produce the maximum modulation

current the laser type requires over temperature. The

modulation LUT can be programmed in 2°C increments

over the -40°C to +102°C range to provide temperature

compensation for the laser’s modulation. The modulation

DAC’s scaling can be used (with APC scaling) to imple-

ment GPON power leveling with a single LUT that works

for all three power levels.

Ranging of the MOD DAC is possible by programming

a single byte in Table 02h.

BIAS and MOD Output During

Initial Power-Up

On power-up the modulation and bias outputs will

remain off until VCC is above VPOA, a temperature con-

version has been completed, and if the VCC LO ADC

alarm is enabled, then a VCC conversion above the

customer defined VCC low alarm level has cleared the

VCC low alarm. Once all of these conditions are satis-

fied, the MOD output will be enabled with the value

determined by the temperature conversion and the

modulation LUT.

When the MOD output is enabled and BEN is high, the

IBIAS DAC output will be turned on to a value equal to

ISTEP (see above). The start-up algorithm checks if this

bias current causes a feedback voltage above the APC

set-point, and if it does not it continues increasing the

IBIAS by ISTEP until the APC set-point is exceeded.

When the APC set point is exceeded, the device will

begin a binary search to quickly reach the bias current

corresponding to the proper power level. After the bina-

ry search is completed the APC integrator is enabled,

and single LSB steps are taken to tightly control the

average power.

All quick-trip and ADC alarm flags are masked until the

binary search is completed. However, the BIAS MAX

alarm is monitored during this time to prevent the bias

output from exceeding MAX IBIAS. During the bias cur-

rent initialization, the bias current is not allowed to

exceed MAX IBIAS. If this occurs during the ISTEP

sequence then the binary search routine is enabled. If

MAX IBIAS is exceeded during the binary search, then

the next smaller step is activated. ISTEP or binary incre-

ments that would cause IBIAS to exceed MAX IBIAS are

not taken. Many of the alarm sources are likely to trip

POWER-UP TIMING

VPOA

VCC

tON

MOD

VOLTAGE

BIAS

CURRENT

4x ISTEP

3x ISTEP

2x ISTEP

ISTEP

tSEARCH

BINARY SEARCH

APC

INTEGRATOR

ON

BIAS

SAMPLE

Figure 1. DS1863 Power-Up.

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