DS1873 查看數據表（PDF） - Maxim Integrated
零件编号
产品描述 (功能)
生产厂家
DS1873 Datasheet PDF : 85 Pages
| |||
SFP+ Controller with Analog LDD Interface
I2C AC ELECTRICAL CHARACTERISTICS
(VCC = +2.85V to +3.9V, TA = -40°C to +95°C, timing referenced to VIL(MAX) and VIH(MIN), unless otherwise noted.) (See Figure 16.)
PARAMETER
SCL Clock Frequency
Clock Pulse-Width Low
Clock Pulse-Width High
Bus-Free Time Between STOP and START
Condition
START Hold Time
START Setup Time
Data Out Hold Time
Data In Setup Time
Rise Time of Both SDA and SCL Signals
Fall Time of Both SDA and SCL Signals
STOP Setup Time
EEPROM Write Time
Capacitive Load for Each Bus Line
SYMBOL
CONDITIONS
fSCL
tLOW
tHIGH
(Note 10)
tBUF
tHD:STA
tSU:STA
tHD:DAT
tSU:DAT
tR
tF
tSU:STO
tW
CB
(Note 11)
(Note 11)
(Note 12)
MIN TYP
0
1.3
0.6
1.3
0.6
0.6
0
100
20 + 0.1CB
20 + 0.1CB
0.6
MAX
400
0.9
300
300
20
400
UNITS
kHz
μs
μs
μs
μs
μs
μs
ns
ns
ns
μs
ms
pF
NONVOLATILE MEMORY CHARACTERISTICS
(VCC = +2.85V to +3.9V, unless otherwise noted.)
PARAMETER
EEPROM Write Cycles
SYMBOL
At +25°C
At +85°C
CONDITIONS
MIN TYP
200,000
50,000
MAX UNITS
Note 1: All voltages are referenced to ground. Current into the IC is positive, and current out of the IC is negative.
Note 2: Inputs are at supply rail. Outputs are not loaded.
Note 3: This parameter is guaranteed by design.
Note 4: Full-scale is user programmable.
Note 5: A temperature conversion is completed and the MOD DAC value is recalled from the LUT and VCC has been measured to
be above VCC LO alarm.
Note 6: The sampling time is 1.6µs per cycle. Each input is sampled every 8 cycles.
Note 7: This specification is the time it takes from MON3 voltage falling below the LLOS trip threshold to LOSOUT asserted high.
Note 8: This specification is the time it takes from MON3 voltage rising above the HLOS trip threshold to LOSOUT asserted low.
Note 9: Assuming an appropriate initial step is programmed that would cause the power to exceed the APC set point within four
steps, the bias output will be within 3% within the time specified by the binary search time. See the BIAS and MOD Output
Control During Power-Up section.
Note 10: I2C interface timing shown is for fast mode (400kHz). This device is also backward compatible with I2C standard mode
timing.
Note 11: CB—the total capacitance of one bus line in pF.
Note 12: EEPROM write begins after a STOP condition occurs.
8 _______________________________________________________________________________________
Share Link: 