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DS1875 查看數據表(PDF) - Maxim Integrated

零件编号
产品描述 (功能)
生产厂家
DS1875
MaximIC
Maxim Integrated MaximIC
DS1875 Datasheet PDF : 92 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
PON Triplexer and SFP Controller
I2C TIMING SPECIFICATIONS
(VCC = +2.85V to +3.9V, TA = -40°C to +95°C, timing referenced to VIL(MAX) and VIH(MIN).) (See Figure 15.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
SCL Clock Frequency
Clock Pulse-Width Low
Clock Pulse-Width High
Bus-Free Time Between STOP
and START Condition
START Hold Time
START Setup Time
Data in Hold Time
Data in Setup Time
Capacitive Load for Each Bus Line
Rise Time of Both SDA and SCL
Signals
Fall Time of Both SDA and SCL
Signals
STOP Setup Time
EEPROM Write Time
fSCL
tLOW
tHIGH
tBUF
tHD:STA
tSU:STA
tHD:DAT
tSU:DAT
CB
tR
tF
tSU:STO
tW
(Note 12)
(Note 13)
(Note 13)
(Note 14)
0
1.3
0.6
1.3
0.6
0.6
0
100
20 +
0.1CB
20 +
0.1CB
0.6
400
kHz
μs
μs
μs
μs
μs
0.9
μs
ns
400
pF
300
ns
300
ns
μs
20
ms
Note 1: All voltages are referenced to ground. Current into IC is positive, and current out of the IC is negative.
Note 2: Digital inputs are at rail. FETG is disconnected. SDA = SCL = VCC. SW, DAC1, and M4DAC are not loaded.
Note 3: See the Safety Shutdown (FETG) Output section for details.
Note 4: Eight ranges allow the full scale to change from 625mV to 2.5V.
Note 5: Eight ranges allow the full scale to change from 312.5mV to 1.25V.
Note 6: This specification applies to the expected full-scale value for the selected range. See the COMP RANGING register
description for available full-scale ranges.
Note 7: The output impedance of the DS1875 is proportional to its scale setting. For instance, if using the 1/2 scale, the output
impedance would be approximately 1.56kΩ.
Note 8: This specification applies to the expected full-scale value for the selected range. See the MOD RANGING register
description for available full-scale ranges.
Note 9: The switching frequency is selectable between four values: 131.25kHz, 262.5kHz, 525kHz, and 1050kHz.
Note 10: See the APC and Quick-Trip Shared Comparator Timing section for details.
Note 11: Guaranteed by design.
Note 12: I2C interface timing shown is for fast-mode (400kHz) operation. This device is also backward compatible with I2C stan-
dard mode.
Note 13: CB—Total capacitance of one bus line in pF.
Note 14: EEPROM write begins after a STOP condition occurs.
_______________________________________________________________________________________ 9

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