DS2016-100 查看數據表（PDF） - Dallas Semiconductor -> Maxim Integrated
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DS2016-100 Datasheet PDF : 9 Pages
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DS2016
TIMING DIAGRAM: DATA RETENTION - POWER-UP, POWER-DOWN Figure 1
SEE NOTE 8
NOTES:
1. WE is high for read cycles.
2. OE = VIH or VIL. If OE = VIH during write cycle, the output buffers remain in a high impedance
state.
3. tWP is specified as the logical AND of CE and WE . tWP is measured from the latter of CE or WE
going low to the earlier of CE or WE going high.
4. tDH and tDS are measured from the earlier of CE or WE going high.
5. If the CE low transition occurs simultaneously with or later than the WE low transition, the
output buffers remain in a high impedance state.
6. If the CE high transition occurs prior to or simultaneously with the WE high transition, the output
buffers remain in a high impedance state.
7. If WE is low or the WE low transition occurs prior to or simultaneously with the CE low
transition, the output buffers remain in a high impedance state.
8. If the VIH level of CE is 2.0V during the period that VCC voltage is going down from 4.5V to
2.7V, ICCS1 current flows.
9. The DS2016 maintains full operation from 5.5V to 2.7V. The electrical characteristics tables show
two tested and guaranteed points of operation. For operation between 4.5V and 3.5 volts, use the
composite worst case characteristics from both 5V and 3V operation for design purposes.
DC TEST CONDITIONS
Outputs Open
All voltages are referenced to ground.
AC TEST CONDITIONS
Output Load: 100 pF + 1TTL Gate
Input Pulse Levels: 0V - 3.0V
Timing Measurement Reference Levels
Input: 1.5V
Output: 1.5V
Input Pulse Rise and Fall Times: 5 ns
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