DS2151 查看數據表（PDF） - Dallas Semiconductor -> Maxim Integrated

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DS2151

T1 Single-Chip Transceiver

Dallas Semiconductor -> Maxim Integrated 

DS2151Q REGISTER MAP (continued)

63

R Receive Signaling Register 4.

73

64

R Receive Signaling Register 5.

74

65

R Receive Signaling Register 6.

75

66

R Receive Signaling Register 7.

76

67

R Receive Signaling Register 8.

77

68

R Receive Signaling Register 9.

78

69

R Receive Signaling Register 10.

79

6A

R Receive Signaling Register 11.

7A

6B

R Receive Signaling Register 12.

7B

6C R/W Receive Channel Blocking

7C

Register 1.

6D R/W Receive Channel Blocking

7D

Register 2.

6E R/W Receive Channel Blocking

7E

Register 3.

6F R/W Interrupt Mask Register 2.

7F

DS2151Q

R/W Transmit Signaling Register 4.

R/W Transmit Signaling Register 5.

R/W Transmit Signaling Register 6.

R/W Transmit Signaling Register 7.

R/W Transmit Signaling Register 8.

R/W Transmit Signaling Register 9.

R/W Transmit Signaling Register 10.

R/W Transmit Signaling Register 11.

R/W Transmit Signaling Register 12.

R/W Line Interface Control Register.

R/W Test Register. (2)

R/W Transmit FDL Register.

R/W Interrupt Mask Register 1.

NOTES:

1. Address 25 also contains Multiframe Out of Sync Count Register 1.

2. The Test Register is used only by the factory; this register must be cleared (set to all 0s) on power-up

initialization to insure proper operation.

2.0 PARALLEL PORT

The DS2151Q is controlled via a multiplexed bidirectional address/data bus by an external

microcontroller or microprocessor. The DS2151Q can operate with either Intel or Motorola bus timing

configurations. If the BTS pin is tied low, Intel timing will be selected; if tied high, Motorola timing will

be selected. All Motorola bus signals are listed in parenthesis (). See the timing diagrams in the A.C.

Electrical Characteristics for more details. The multiplexed bus on the DS2151Q saves pins because the

address information and data information share the same signal paths. The addresses are presented to the

pins in the first portion of the bus cycle and data will be transferred on the pins during second portion of

the bus cycle. Addresses must be valid prior to the falling edge of ALE (AS), at which time the

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