DS2740B 查看數據表（PDF） - Dallas Semiconductor -> Maxim Integrated
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DS2740B Datasheet PDF : 15 Pages
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PART
DS2740
DS2740B
VIS1- VIS2
±204.8mVh
ACR RANGE
20mW
RSNS
15mW
10mW
±10.24Ah ±13.65Ah ±20.48Ah
5mW
±40.96Ah
DS2740
MEMORY
The DS2740 has memory space with registers for instrumentation, status, and control. When the MSB of
a two-byte register is read, both the MSB and LSB are latched and held for the duration of the read data
command to prevent updates during the read and ensure synchronization between the two register bytes.
For consistent results, always read the MSB and the LSB of a two-byte register during the same read data
command sequence.
Table 3. MEMORY MAP
ADDRESS (HEX)
DESCRIPTION
00
Reserved
01
Status Register
02 to 07
Reserved
08
Special Feature Register
09 to 0D
Reserved
0E
Current Register MSB
0F
Current Register LSB
10
Accumulated Current Register MSB
11
Accumulated Current Register LSB
12 to FF
Reserved
READ/WRITE
—
R
—
R/W
—
R
R
R/W
R/W
—
STATUS REGISTER
The format of the status register is shown in Figure 5. The function of each bit is described in detail in the
following paragraphs.
Figure 5. STATUS REGISTER FORMAT
BIT 7
X
BIT 6
SMOD
ADDRESS 01
BIT 5 BIT 4 BIT 3
X RNAOP X
BIT 2
X
BIT 1
X
BIT 0
X
SMOD—SLEEP Mode Enable. A value of 1 allows the DS2740 to enter sleep mode when DQ is low for
2s. A value of 0 disables DQ related transitions to sleep mode. The power-up default of SMOD = 0.
RNAOP—Read Net Address Opcode. A value of 0 in this bit sets the opcode for the read net address
command to 33h, while a 1 sets the opcode to 39h. The power-up default of RNAOP = 0.
X—Reserved bits.
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