DS2746G 查看數據表（PDF） - Dallas Semiconductor -> Maxim Integrated

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DS2746G

Low-Cost 2-Wire Battery Monitor with Ratiometric A/D Inputs

Dallas Semiconductor -> Maxim Integrated 

DS2746 Low-Cost 2-Wire Battery Monitor

SCL, SDA

Input Capacitance:

SCL, SDA

Bus Low Timeout

CBUS

tSLEEP

VPIN = 0.4V

(Note 3)

50

pF

1.5

2.2

S

DC ELECTRICAL CHARACTERISTICS: 2-WIRE INTERFACE

(VDD = 2.5V to 5.5V, TA = -20°C to +70°C.)

PARAMETER

SYMBOL

CONDITIONS

MIN TYP

SCL Clock Frequency

Bus Free Time Between a

STOP and START Condition

Hold Time (Repeated)

START Condition

Low Period of SCL Clock

High Period of SCL Clock

Setup Time for a Repeated

START Condition

Data Hold Time

Data Setup Time

Rise Time of Both SDA and

SCL Signals

Fall Time of Both SDA and

SCL Signals

Setup Time for STOP

Condition

Spike Pulse Widths

Suppressed by Input Filter

Capacitive Load for Each Bus

Line

SCL, SDA Input Capacitance

fSCL

tBUF

tHD:STA

tLOW

tHIGH

tSU:STA

tHD:DAT

tSU:DAT

tR

tF

tSU:STO

tSP

CB

CBIN

(Note 4)

(Note 5)

(Note 6, 7)

(Note 6)

(Note 8)

(Note 9)

0

1.3

0.6

1.3

0.6

0.6

0

100

20 + 0.1CB

20 + 0.1CB

0.6

0

MAX

400

0.9

300

300

50

400

60

UNITS

KHz

µs

µs

µs

µs

µs

µs

ns

ns

ns

µs

ns

pF

pF

Note 1:

Note 2:

Note 3:

Note 4:

Note 5:

Note 6:

Note 7:

Note 8:

Note 9:

Note 10:

Note 11:

All voltages are referenced to VSS.

Offset specified after auto-calibration cycle and Current Offset Bias register = 0x00.

The DS2746 enters the sleep mode 1.5s to 2.2s after ( SCL < Vil.) AND ( SDA < Vil ).

Timing must be fast enough to prevent the DS2746 from entering sleep mode due to bus low for period > tSLEEP.

fSCL must meet the minimum clock low time plus the rise/fall times.

The maximum tHD:DAT has only to be met if the device does not stretch the LOW period (tLOW) of the SCL signal.

This device internally provides a hold time of at least 100ns for the SDA signal (referred to the VIHmin of the SCL signal) to

bridge the undefined region of the falling edge of SCL.

Filters on SDA and SCL suppress noise spikes at the input buffers and delay the sampling instant.

Cb – total capacitance of one bus line in pF.

The AINGERR spec is only valid when this equation is satisfied: (VAINx + 2VOUT) ≤ (11.6V - (TA - 25°C)10mV/°C). See Figure 1.

Accuracy specification valid for VSS - SNS ≥ ±2.5mV, below which offset error is dominant.

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