DS2711(2008) 查看數據表（PDF） - Maxim Integrated
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DS2711 Datasheet PDF : 15 Pages
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DS2711/DS2712: Loose Cell NiMH Charger
Undervoltage Lockout (UVLO)
The UVLO circuit serves as a power-up and brownout detector by monitoring VDD to prevent charging until VDD
rises above VUVLO, or when VDD drops below VUVLO - VHYS. If UVLO is active, charging is prevented, the state
machine is forced to the RESET state, and all charge timers are reset. A 10μs deglitch circuit provides noise
immunity.
Internal Oscillator and Clock Generation
An internal oscillator provides the main clock source used to generate timing signals for internal chip operation. The
precharge timer, hold-off timers, and timings for CC1/CC2 operation and cell testing are derived from this timebase.
In case the internal clock should ever fail, a watchdog detection circuit halts charging. The watchdog safety circuit
and charge timer set by the TMR pin are derived from separate oscillators than the main clock source.
Current-Sense Amplifier (DS2711)
An error amplifier block provides several options to regulate the charge current. The 20mA open-drain output can
drive a PMOS or PNP pass element for linear regulation, or the output can drive an optocoupler for isolated
feedback to a primary-side PWM controller. The VN0 pin is a remote-sense return and should be connected to the
grounded side of the sense resistor using a separate, insulated conductor.
Figure 6. Current-Sense Amplifier Response
1.20
0
1.00
-50
Gain
Phase
0.80
-100
0.60
-150
0.40
-200
0.20
-250
0.00
-300
10 1
10 2
10 3
10 4
10 5
10 6
10 7
Frequency (Hertz)
The open-loop amplifier response shown in Figure 6 was measured with ICSOUT = -1mA. An error signal between
the current-sense signal (across a sense resistor) and the 0.125V internal reference is produced so the voltage
across the sense resistor is maintained at VIREF in a closed-loop circuit.
Current-Sense Comparator (DS2712)
The comparator in the DS2712 switches between ON and OFF and is capable of driving a PNP bipolar or a PMOS
transistor, enabling the use of a switched-mode power stage. Hysteresis on the comparator input provides noise
rejection. In the closed-loop regulation circuit of Figure 5, the comparator regulates voltage across the sense
resistor to a DC average of:
VRSNS = VIREF - 0.5 x VHYS-COMP = 0.125V
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