DS2745 查看數據表（PDF） - Maxim Integrated

零件编号

产品描述 (功能)

生产厂家

DS2745

Low-Cost I2C Battery Monitor

Maxim Integrated 

Note 1:

Note 2:

Note 3:

Note 4:

Note 5:

Note 6:

Note 7:

Note 8:

Note 9:

Note 10:

Note 11:

Note 12:

DS2745 Low-Cost I2C Battery Monitor

All voltages are referenced to VSS.

Offset specified after auto-calibration cycle and Current Offset Bias register (COBR) set to 00h.

To properly enter sleep mode, SMOD=1, and the application should hold SDA and SCL low for longer

than the maximum tSLEEP.

NBEN = 0, Current Offset Bias Register (COBR) set to 00h, and Accumulation Bias Register (ABR)

set to 00h.

Parameters guaranteed by design.

Timing must be fast enough to prevent the DS2745 from entering sleep mode due to SDA,SCL low

for period >

tSLEEP.

fSCL must meet the minimum clock low time plus the rise/fall times.

The maximum tHD:DAT has only to be met if the device does not stretch the LOW period (tLOW) of the

SCL

signal.

This device internally provides a hold time of at least 100 ns for the SDA signal (referred to the

VIHmin of

the SCL signal) to bridge the undefined region of the falling edge of SCL.

Filters on SDA and SCL suppress noise spikes at the input buffers and delay the sampling instant.

CBtotal capacitance of one bus line in pF.

The first voltage measurement after writing the ACR or after device POR is not valid.

Figure 1. I2C Bus Timing Diagram

4 of 15

Share Link: