DS3231SN/TU0026R 查看數據表（PDF） - Maxim Integrated
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DS3231SN/TU0026R Datasheet PDF : 19 Pages
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Extremely Accurate I2C-Integrated
RTC/TCXO/Crystal
Figure 1. Timekeeing Registers
ADDRESS
00H
01H
BIT 7
MSB
0
0
02H
0
03H
0
04H
0
BIT 6 BIT 5
BIT 4
12/24
0
0
10 Seconds
10 Minutes
AM/PM
10 Hour
10 Hour
0
0
10 Date
BIT 3
0
BIT 2 BIT 1
Seconds
Minutes
BIT 0
LSB
Hour
Day
Date
FUNCTION
Seconds
Minutes
Hours
Day
Date
RANGE
00–59
00–59
1–12 + AM/PM
00–23
1–7
00–31
05H
Century
0
0
10 Month
Month
Month/
Century
01–12 +
Century
06H
10 Year
07H
A1M1
10 Seconds
08H
A1M2
10 Minutes
09H
A1M3
12/24
AM/PM
10 Hour
10 Hour
0AH
A1M4 DY/DT
10 Date
Year
Seconds
Minutes
Hour
Day
Date
Year
Alarm 1 Seconds
Alarm 1 Minutes
Alarm 1 Hours
Alarm 1 Day
Alarm 1 Date
00–99
00–59
00–59
1–12 + AM/PM
00–23
1–7
1–31
0BH
A2M2
10 Minutes
Minutes
Alarm 2 Minutes
00–59
0CH
A2M3
12/24
AM/PM
10 Hour
10 Hour
Hour
Alarm 2 Hours
1–12 + AM/PM
00–23
0DH
A2M4 DY/DT
10 Date
Day
Date
Alarm 2 Day
Alarm 2 Date
1–7
1–31
0EH
EOSC BBSQW CONV
RS2
RS1 INTCN A2IE A1IE
Control
—
0FH
OSF
0
0
0
EN32kHz BSY A2F A1F Control/Status
—
10H
SIGN DATA DATA
DATA
DATA DATA DATA DATA Aging Offset
—
11H
SIGN DATA DATA
DATA
DATA DATA DATA DATA MSB of Temp
—
12H
DATA DATA
0
0
0
0
0
0
LSB of Temp
—
Note: Unless otherwise specified, the registers’ state is not defined when power is first applied.
DS3231 I2C interface may be placed into a known state
by toggling SCL until SDA is observed to be at a high
level. At that point the microcontroller should pull SDA
low while SCL is high, generating a START condition.
Clock and Calendar
The time and calendar information is obtained by read-
ing the appropriate register bytes. Figure 1 illustrates the
RTC registers. The time and calendar data are set or ini-
tialized by writing the appropriate register bytes. The con-
tents of the time and calendar registers are in the
binary-coded decimal (BCD) format. The DS3231 can be
run in either 12-hour or 24-hour mode. Bit 6 of the hours
register is defined as the 12- or 24-hour mode select bit.
When high, the 12-hour mode is selected. In the 12-hour
mode, bit 5 is the AM/PM bit with logic-high being PM. In
the 24-hour mode, bit 5 is the second 10-hour bit (20–23
hours). The century bit (bit 7 of the month register) is tog-
gled when the years register overflows from 99 to 00.
The day-of-week register increments at midnight.
Values that correspond to the day of week are user-
defined but must be sequential (i.e., if 1 equals
Sunday, then 2 equals Monday, and so on). Illogical
time and date entries result in undefined operation.
When reading or writing the time and date registers, sec-
ondary (user) buffers are used to prevent errors when
the internal registers update. When reading the time and
date registers, the user buffers are synchronized to the
internal registers on any START and when the register
pointer rolls over to zero. The time information is read
from these secondary registers, while the clock contin-
ues to run. This eliminates the need to reread the regis-
ters in case the main registers update during a read.
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