DS34T101 查看數據表（PDF） - Maxim Integrated
零件编号
产品描述 (功能)
生产厂家
DS34T101 Datasheet PDF : 16 Pages
| |||
ABRIDGED DATA SHEET
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
TDMoP Bundles
64 independent bundles, each can be assigned to any TDM interface
Each bundle carries a data stream from one TDM interface over IP/MPLS/Ethernet PSN from TDMoP source
device to TDMoP destination device
Each bundle may be for N x 64kbps, an entire E1, T1, E3, T3 or STS-1, or an arbitrary serial data stream
Each bundle is uni-directional (but frequently coupled with opposite-direction bundle for bidirectional
communication)
Multiple bundles can be transported between TDMoP devices
Multiple bundles can be assigned to the same TDM interface
Each bundle is independently configured with its own:
o Transmit and receive queues
o Configurable receive-buffer depth
o Optional connection-level redundancy (SAToP, AAL1, CESoPSN only).
Each bundle can be assigned to one of the payload-type machines or to the CPU
For E1/T1 the device provides internal bundle cross-connect functionality, with DS0 resolution
TDMoP Clock Recovery
Sophisticated TDM clock recovery machines, one for each TDM interface, allow end-to-end TDM clock
synchronization, despite the packet delay variation of the IP/MPLS/Ethernet network
The following clock recovery modes are supported:
o Adaptive clock recovery
o Common clock (using RTP)
o External clock
o Loopback clock
The clock recovery machines provide both fast frequency acquisition and highly accurate phase tracking:
o Jitter and wander of the recovered clock are maintained at levels that conform to G.823/G.824 traffic or
synchronization interfaces. (For adaptive clock recovery, the recovered clock performance depends on
packet network characteristics.)
o Short-term frequency accuracy (1 second) is better than 16 ppb (using OCXO reference), or 100 ppb
(using TCXO reference)
o Capture range is ±90 ppm
o Internal synthesizer frequency resolution of 0.5 ppb
o High resilience to packet loss and misordering, up to 2% without degradation of clock recovery
performance
o Robust to sudden significant constant delay changes
o Automatic transition to holdover when link break is detected
TDMoP Delay Variation Compensation
Configurable jitter buffers compensate for delay variation introduce by the IP/MPLS/Ethernet network
Large maximum jitter buffer depths:
o E1: up to 256 ms
o T1 unframed: up to 340 ms
o T1 framed: up to 256 ms
o T1 framed with CAS: up to 192 ms
o E3: up to 60 ms
o T3: up to 45 ms
o STS-1: up to 40 ms.
Packet reordering is performed for SAToP and CESoPSN bundles within the range of the jitter buffer
Packet loss is compensated by inserting either a pre-configured conditioning value or the last received value.
11 of 16
Share Link: 