DSP56303 Overview
Program memory expansion to one 256 K × 24-bit words memory space using the
standard external address lines
Further features of external memory include the following:
External memory expansion port
Simultaneous glueless interface to static random access memory (SRAM) and dynamic
random access memory (DRAM)
1.7 Internal Buses
To provide data exchange between the blocks, the DSP56303 implements the following buses:
Peripheral I/O expansion bus to peripherals
Program memory expansion bus to program ROM
X memory expansion bus to X memory
Y memory expansion bus to Y memory
Global data bus between PCU and other core structures
Program data bus for carrying program data throughout the core
X memory data bus for carrying X data throughout the core
Y memory data bus for carrying Y data throughout the core
Program address bus for carrying program memory addresses throughout the core
X memory address bus for carrying X memory addresses throughout the core
Y memory address bus for carrying Y memory addresses throughout the core.
The block diagram in Figure 1-1 illustrates these buses among other components. All internal
buses on the DSP56300 family members are 24-bit buses. The program data bus is also a 24-bit
bus.
1-10
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor