DSPIC33FJ32GP202(2007) 查看數據表（PDF） - Microchip Technology

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DSPIC33FJ32GP202
(Rev.:2007)

High-Performance, 16-Bit Microcontrollers

Microchip Technology 

dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304

2.4 CPU Control Registers

CPU control registers include:

• SR: CPU Status Register

• CORCON: CORE Control Register

REGISTER 2-1: SR: CPU STATUS REGISTER

R-0

OA

bit 15

R-0

R/C-0

R/C-0

OB

SA(1)

SB(1)

R/W-0(2)

R/W-0(3)

R/W-0(3)

R-0

IPL<2:0>(2)

RA

bit 7

R-0

OAB

R/W-0

N

R/C-0

SAB

R/W-0

OV

R -0

DA

R/W-0

Z

R/W-0

DC

bit 8

R/W-0

C

bit 0

Legend:

C = Clear only bit

S = Set only bit

‘1’ = Bit is set

R = Readable bit

W = Writable bit

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n = Value at POR

x = Bit is unknown

bit 15

bit 14

bit 13

bit 12

bit 11

bit 10

bit 9

OA: Accumulator A Overflow Status bit

1 = Accumulator A overflowed

0 = Accumulator A has not overflowed

OB: Accumulator B Overflow Status bit

1 = Accumulator B overflowed

0 = Accumulator B has not overflowed

SA: Accumulator A Saturation ‘Sticky’ Status bit(1)

1 = Accumulator A is saturated or has been saturated at some time

0 = Accumulator A is not saturated

SB: Accumulator B Saturation ‘Sticky’ Status bit(1)

1 = Accumulator B is saturated or has been saturated at some time

0 = Accumulator B is not saturated

OAB: OA || OB Combined Accumulator Overflow Status bit

1 = Accumulators A or B have overflowed

0 = Neither Accumulators A or B have overflowed

SAB: SA || SB Combined Accumulator ‘Sticky’ Status bit

1 = Accumulators A or B are saturated or have been saturated at some time in the past

0 = Neither Accumulator A or B are saturated

Note: This bit can be read or cleared (not set). Clearing this bit will clear SA and SB.

DA: DO Loop Active bit

1 = DO loop in progress

0 = DO loop not in progress

Note 1:

2:

3:

This bit can be read or cleared (not set).

The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority

Level. The value in parentheses indicates the IPL if IPL<3> = 1. User interrupts are disabled when

IPL<3> = 1.

The IPL<2:0> Status bits are read only when NSTDIS = 1 (INTCON1<15>).

DS70290A-page 16

Preliminary

© 2007 Microchip Technology Inc.

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