DS_M368L3223DTL 查看數據表（PDF） - Samsung
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DS_M368L3223DTL Datasheet PDF : 12 Pages
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M368L3223DTL
184pin Unbuffered DDR SDRAM MODULE
DDR SDRAM IDD spec table
Symbol
IDD0
B3(DDR333@CL=2.5) A2(DDR266@CL=2)
720
640
B0(DDR266@CL=2.5)
640
Unit
mA
Notes
IDD1
960
IDD2P
24
880
880
mA
24
24
mA
IDD2F
200
IDD2Q
160
IDD3P
280
160
160
mA
144
144
mA
240
240
mA
IDD3N
IDD4R
440
1360
360
1120
360
mA
1120
mA
IDD4W
IDD5
Normal
IDD6
Low power
IDD7A
1360
1440
24
12
2600
1120
1320
24
12
2240
1120
1320
24
12
2240
mA
mA
mA
mA
Optional
mA
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
AC OPERATING CONDITIONS
Parameter/Condition
Input High (Logic 1) Voltage, DQ, DQS and DM signals
Input Low (Logic 0) Voltage, DQ, DQS and DM signals.
Input Differential Voltage, CK and CK inputs
Input Crossing Point Voltage, CK and CK inputs
Symbol
VIH(AC)
VIL(AC)
VID(AC)
VIX(AC)
Min
VREF + 0.31
0.7
0.5*VDDQ-0.2
Max
VREF - 0.31
VDDQ+0.6
0.5*VDDQ+0.2
Unit
V
V
V
V
Note
3
3
1
2
Note 1. VID is the magnitude of the difference between the input level on CK and the input on CK.
2. The value of VIX is expected to equal 0.5*V DDQ of the transmitting device and must track variations in the DC level of the same.
3. These parameters should be tested at the pim on actual components and may be checked at either the pin or the pad in simula-
tion. the AC and DC input specificatims are refation to a Vref envelope that has been bandwidth limited 20MHz.
AC OPERATING TEST CONDITIONS (VDD=2.5V, VDDQ=2.5V, T A= 0 to 70 °C)
Parameter
Input reference voltage for Clock
Value
0.5 * VDDQ
Input signal maximum peak swing
Input Levels(VIH/VIL)
1.5
VREF+0.31/VREF-0.31
Input timing measurement reference level
VREF
Output timing measurement reference level
Output load condition
Vtt
See Load Circuit
Unit
V
V
V
V
V
Note
Rev. 0.2 May. 2002
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