AS4LC1M16E5-50JC 查看數據表（PDF） - Alliance Semiconductor

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AS4LC1M16E5-50JC

3V 1M×16 CMOS DRAM (EDO)

Alliance Semiconductor 

AS4LC1M16E5

®

DC electrical characteristics

Parameter

Symbol

Input leakage current

IIL

Output leakage current

IOL

Operating power

supply current

ICC1

TTL standby power

supply current

ICC2

Average power supply

current, RAS refresh

ICC3

mode or CBR

EDO page mode average

power supply current

ICC4

CMOS standby power

supply current

ICC5

Output voltage

VOH

VOL

CAS before RAS refresh

current

ICC6

Self refresh current

ICC7

Shaded areas indicate advance information.

Test conditions

0V ≤ Vin ≤ VCC (max)

Pins not under test = 0V

DOUT disabled, 0V ≤ Vout ≤ VCC (max)

RAS, UCAS, LCAS, Address cycling;

tRC=min

RAS = UCAS = LCAS ≥ VIH,

all other inputs at VIH or VIL

RAS cycling, UCAS = LCAS ≥ VIH,

tRC = min of RAS low after XCAS low.

RAS = VIL, UCAS or LCAS,

address cycling: tHPC = min

RAS = UCAS = LCAS = VCC - 0.2V,

F=0

IOUT = -5.0 mA

IOUT = 4.2 mA

RAS, UCAS or LCAS cycling, tRC = min

RAS = UCAS = LCAS ≤ 0.2V,

WE = OE ≥ VCC - 0.2V,

all other inputs at 0.2V or

VCC - 0.2V

-50

Min Max

-2 +2

-2 +2

– 140

– 2.0

– 80

– 85

–1

2.4 –

– 0.4

– 80

– 0.5

-60

Min Max Unit Notes

-2 +2 µA

-2 +2 µA

– 130 mA 4,5

– 2.0 mA

– 70 mA 4

– 75 mA 4, 5

– 1 mA

2.4 – V

– 0.4 V

– 70 mA

– 0.5 mA

4/11/01

Alliance Semiconductor

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