EBE21AD4AGFA 查看數據表（PDF） - Elpida Memory, Inc

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EBE21AD4AGFA

2GB Registered DDR2 SDRAM DIMM

Elpida Memory, Inc 

Differential Clock Net Wiring (CK0, /CK0)

0ns (nominal)

PLL

OUT1

CK0

/CK0

120Ω

IN

120Ω

C

OUT'N'

Feedback in

Feedback out

EBE21AD4AGFA

SDRAM

SDRAM

120Ω

Register 1

C

Register 3

120Ω

Register 2

C

Register 4

120Ω

Notes: 1. The clock delay from the input of the PLL clock to the input of any SDRAM or register willl

be set to 0ns (nominal).

2. Input, output and feedback clock lines are terminated from line to line as shown, and not

from line to ground.

3. Only one PLL output is shown per output type. Any additional PLL outputs will be wired

in a similar manner.

4. Termination resistors for the PLL feedback path clocks are located as close to the

input pin of the PLL as possible.

Preliminary Data Sheet E0866E11 (Ver. 1.1)

9

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