EDE1108AASE 查看數據表（PDF） - Elpida Memory, Inc
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EDE1108AASE Datasheet PDF : 65 Pages
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EDE1104AASE, EDE1108AASE
max.
Parameter
Symbol Grade × 4
×8
Unit
Test condition
-6E TBD
TBD
Auto-refresh current IDD5 -5C TBD
TBD
mA
-4A 360
TBD
tCK = tCK (IDD);
Refresh command at every tRFC (IDD) interval;
CKE is H, /CS is H between valid commands;
Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
Self-refresh current IDD6
Self Refresh Mode;
CK and /CK at 0V;
15
TBD
mA
CKE ≤ 0.2V;
Other control and address bus inputs are FLOATING;
Data bus inputs are FLOATING
Operating current
-6E TBD
TBD
IDD7 -5C TBD
TBD
mA
(Bank interleaving)
-4A 350
TBD
all bank interleaving reads, IOUT = 0mA;
BL = 4, CL = CL(IDD), AL = tRCD (IDD) −1 × tCK (IDD);
tCK = tCK (IDD), tRC = tRC (IDD), tRRD = tRRD(IDD),
tRCD = 1 × tCK (IDD);
CKE is H, CS is H between valid commands;
Address bus inputs are STABLE during DESELECTs;
Data pattern is same as IDD4W;
Notes: 1. IDD specifications are tested after the device is properly initialized.
2. Input slew rate is specified by AC Input Test Condition.
3. IDD parameters are specified with ODT disabled.
4. Data bus consists of DQ, DM, DQS, /DQS, RDQS and /RDQS. IDD values must be met with all
combinations of EMRS bits 10 and 11.
5. Definitions for IDD
L is defined as VIN ≤ VIL (AC) (max.)
H is defined as VIN ≥ VIH (AC) (min.)
STABLE is defined as inputs stable at an H or L level
FLOATING is defined as inputs at VREF = VDDQ/2
SWITCHING is defined as:
inputs changing between H and L every other clock cycle (once per two clocks) for address and control
signals, and inputs changing between H and L every other data transfer (once per clock) for DQ signals
not including masks or strobes.
6. Refer to AC Timing for IDD Test Conditions.
AC Timing for IDD Test Conditions
For purposes of IDD testing, the following parameters are to be utilized.
DDR2-667
DDR2-533
Parameter
CL(IDD)
5-5-5
5
4-4-4
4
tRCD(IDD)
15
15
tRC(IDD)
60
60
tRRD(IDD)-×4/×8
7.5
7.5
tCK(IDD)
3
3.75
tRAS (min.)(IDD)
45
45
tRAS (max.)(IDD) 70000
70000
tRP(IDD)
15
15
tRFC(IDD)
127.5
127.5
DDR2-400
3-3-3
3
15
55
7.5
5
40
70000
15
127.5
Unit
tCK
ns
ns
ns
ns
ns
ns
ns
ns
Data Sheet E0404E20 (Ver. 2.0)
8
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