EDE1108AJBG-1 查看數據表（PDF） - Elpida Memory, Inc

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EDE1108AJBG-1

1G bits DDR2 SDRAM

Elpida Memory, Inc 

EDE1108AJBG-1, EDE1116AJBG-1

AC Timing for IDD Test Conditions

For purposes of IDD testing, the following parameters are to be utilized.

DDR2-1066

Parameter

7-7-7

Unit

CL (IDD)

7

tCK

tRCD (IDD)

13.125

ns

tRC (IDD)

58.125

ns

tRRD (IDD)-×8

7.5

ns

tRRD (IDD)-×16

10

ns

tFAW (IDD)-×8

35

ns

tFAW (IDD)-×16

45

ns

tCK (IDD)

1.875

ns

tRAS (min.)(IDD)

45

ns

tRAS (max.)(IDD)

70000

ns

tRP (IDD)

13.125

ns

tRFC (IDD)

127.5

ns

IDD7 Timing Patterns for 8 Banks

The detailed timings are shown in the IDD7 Timing Patterns for 8 Banks tables.

[×8 organization]

Speed bins

Timing Patterns

DDR2-1066

A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D A4 RA4 D D A5 RA5 D D A6 RA6 D D A7 RA7 D D D

DD

[×16 organization]

Speed bins

Timing Patterns

DDR2-1066

A0 RA0 D D D D A1 RA1 D D D D A2 RA2 D D D D A3 RA3 D D D D A4 RA4 D D D D A5 RA5 D D D D A6

RA6 D D D D A7 RA7 D D D D

Remark: A = Active. RA = Read with auto precharge. D = Deselect

Notes: 1. All banks are being interleaved at minimum tRC (IDD) without violating tRRD (IDD) and tFAW (IDD) using

a Burst length = 4.

2. Control and address bus inputs are STABLE during DESELECTs.

3. IOUT = 0mA.

Data Sheet E1733E31 (Ver.3.1)

10

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