White Electronic Designs
EDI88512CA-RP
ADDRESS
DATA I/O
May 2004
Rev. 6
FIG. 2 – TIMING WAVEFORM — READ CYCLE
tAVAV
ADDRESS 1
ADDRESS 2
tAVQV
tAVQX
DATA 1
DATA 2
ADDRESS
CS#
OE#
DATA OUT
tAVAV
tAVQV
tELQV
tELQX
tGLQV
tGLQX
tEHQZ
tGHQZ
READ CYCLE 1 (WE# HIGH; OE#, CS# LOW)
READ CYCLE 2 (WE# HIGH)
FIG. 3 – WRITE CYCLE — WE# CONTROLLED
ADDRESS
CS#
WE#
tAVWL
tAVAV
tAVWH
tELWH
tWHAX
tWLWH
tDVWH
tWHDX
DATA IN
DATA OUT
tWLQZ
DATA VALID
tWHQX
HIGH Z
WRITE CYCLE 1, WE# CONTROLLED
FIG. 4 – WRITE CYCLE — CS# CONTROLLED
ADDRESS
CS#
WE#
DATA IN
DATA OUT
tAVEL
tAVAV
WS32K32-XHX
tAVEH
tELEH
tEHAX
tWLEH
tDVEH
tEHDX
DATA VALID
HIGH Z
WRITE CYCLE 2, CS# CONTROLLED
4
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com