EL2166 查看數據表（PDF） - Intersil
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EL2166 Datasheet PDF : 15 Pages
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EL2166
Open-Loop DC Electrical Specifications
VS = ±15V, RL = 150Ω, TA = 25°C unless otherwise specified (Continued)
LIMITS
PARAMETER
DESCRIPTION
CONDITIONS
TEMP
MIN
TYP MAX UNITS
IDIS, ON
DISABLE Pin Input Current, Pin 8 = +5V
25°C
70
150
µA
IDIS, OFF
DISABLE Pin Input Current, Pin 8 = 0V
25°C
-150
-60
µA
NOTES:
1. Measured from TMIN to TMAX.
2. VCM = ±12.6V for VS = ±15V and TA = 25°C. VCM = ±2.6V for VS = ±5V and TA = 25°C.
3. The supplies are moved from ±5V to ±15V.
4. VOUT = ±7V for VS = ±15V, and VOUT = ±2V for VS = ±5V.
5. A heat sink is required to keep junction temperature below absolute maximum when an output is shorted.
6. The EL2166 will remain ENABLED if pin 8 is either left unconnected or VIH is applied to pin 8.
Closed-Loop AC Electrical Specifications
PARAMETER
DESCRIPTION
BW
-3dB Bandwidth (Note 1)
SR
tR, tF
tPD
OS
tS
dG
Slew Rate (Note 1)(Note 2)
Rise Time, Fall Time (Note 1)
Propagation Delay (Note 1)
Overshoot (Note 1)
0.1% Settling Time (Note 1)
Differential Gain (Note 1)(Note 3)
dP
Differential Phase (Note 1)(Note 3)
tDIS
Disable/Enable Time (Note 4)
VS = ±15V, AV = +2, RF = 560Ω, RL = 150Ω, TA = 25°C unless otherwise noted
LIMITS
CONDITIONS
MIN
TYP
MAX
UNITS
VS = ±15V, AV = +2
VS = ±15V, AV = +1
VS = ±5V, AV = +2
VS = ±5V, AV = +1
RL = 400Ω
VOUT = ±500mV
1000
110
115
95
100
1500
3.2
4.3
MHz
MHz
MHz
MHz
V/µs
ns
ns
VOUT = ±500mV
VOUT = ±10V
AV = ±1, RL = 1k
RL = 150Ω, VS = ±15V
RL = 150Ω, VS = ±5V
RL = 500Ω, VS = ±15V
RL = 500Ω, VS = 5V
RL = 150Ω, VS = ±15V
RL = 150Ω, VS = ±5V
RL = 500Ω, VS = ±15V
RL = 500Ω, VS = 5V
7
35
0.025
0.05
0.01
0.01
0.04
0.02
0.01
0.01
75
%
ns
%
%
%
%
deg (°)
deg (°)
deg (°)
deg (°)
ns
NOTES:
1. All AC tests are performed on a “warmed up” part, except for Slew Rate, which is pulse tested.
2. Slew Rate is with VOUT from +10V to -10V and measured at the 25% and 75% points.
3. DC offset from -0.714V through +0.714V, AC amplitude 286 mVP-P, f = 3.58MHz.
4. Disable/Enable time is defined as the time from when the logic signal is applied to the DISABLE pin to when the output voltage has gone 50%
of the way from its initial to its final value.
3
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