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EL4585C 查看數據表(PDF) - Elantec -> Intersil

零件编号
产品描述 (功能)
生产厂家
EL4585C
ELANTE-ElectronicC
Elantec -> Intersil ELANTE-ElectronicC
EL4585C Datasheet PDF : 16 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
EL4585C
Horizontal Genlock 8 FSC
AC Electrical Characteristics (VDDe5V TAe25 C unless otherwise noted)
Parameter
Conditions
Temp
Min
Typ
Max
VCO Gain 20 MHz
Test circuit 1
25 C
15 5
H-sync S N Ratio
VDDe5V (Note 2)
25 C
35
Jitter
VCXO Oscillator
25 C
1
Jitter
LC Oscillator (Typ)
25 C
10
Note 2 Noisy video signal input to EL4583C H-sync input to EL4585C Test for positive signal lock
Test
Level
V
V
V
V
Units
dB
dB
ns
ns
Pin Description
Pin No Pin Name
Function
16 1 2 Prog A B C
Digital inputs to select d N value for internal counter See table below for values
3
Osc VCO Out Output of internal inverter oscillator Connect to external crystal or LC tank VCO circuit
4
VDD (A)
Analog positive supply for oscillator PLL circuits
5
Osc VCO In Input from external VCO
6
VSS (A)
Analog ground for oscillator PLL circuits
7
Charge Pump Connect to loop filter If the H-sync phase is leading or H-sync frequency l CLKd2N current is
Out
pumped into the filter capacitor to increase VCO frequency If H-sync phase is lagging or frequency
k CLKd2N current is pumped out of the filter capacitor to decrease VCO frequency During coast
mode or when locked charge pump goes to a high impedance state
8
Div Select
Divide select input When high the internal divider is enabled and EXT DIV becomes a test pin
outputting CLKd2N When low the internal divider is disabled and EXT DIV is an input from an
external dN
9
Coast
Tri-state logic input Low(k VCC) e normal mode Hi Z(or to VCC) e fast lock mode
High(l VCC) e coast mode
10
H-sync In
Horizontal sync pulse (CMOS level) input
11
VDD (D)
Positive supply for digital I O circuits
12
Lock Det
Lock Detect output Low level when PLL is locked Pulses high when out of lock
13
Ext Div
External Divide input when DIV SEL is low internal d 2N output when DIV SEL is high
14
VSS (D)
Ground for digital I O circuits
15
CLK Out
Buffered output of the VCO
Prog A
Pin 16
0
0
0
0
1
1
1
1
Table 5 VCO Divisors
Prog B
Pin 1
Prog C
Pin 2
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
Div Value
N
1702
1728
1888
2270
1364
1716
1560
1820
3

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