EL7520ILZ-T13 查看數據表（PDF） - Intersil

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EL7520ILZ-T13

4-Channel DC/DC Controller

Intersil 

EL7520, EL7520A

Pin Descriptions

PIN NUMBER

1

PIN NAME

CDLY

2

DRVB

3

PGND

4

ISAD

5

ISIN

6

DELB

7

SGND

8

FBB

9

CINT

10

VREF

11

FBN

12

DRVN

13

FBL

14

DRVL

15

FBP

16

DRVP

17

EN

18

VDD

19

VDDP

20

PG

FUNCTION DESCRIPTION

With a capacitor connected from this pin to GND sets the delay time for start-up sequence and sets the fault

timeout time

Gate driver output for the external N channel switch; the pulse voltage follows the input voltage

Power GND

With a resistor connected from this pin to GND sets the current limit of the external N channel FET

Sense the drain voltage of the external N channel FET and connected to the internal current limit comparator

Active low control output for optional delay control for external VBOOST P channel FET; when fault is detected,

this pin goes to high

Low noise signal ground

Boost regulator voltage feedback input pin; regulates to 1.2V nominal

VBOOST integrator output, connect 2.2nF to analog GND for PI mode or connect to VREF for P mode operation

Bandgap voltage bypass terminal; bypass with a 0.1µF to analog GND; can be used as charge pump reference

Negative LDO voltage feedback input pin; regulates to 0.2V nominal

Negative LDO base drive; open drain of an internal P channel MOSFET

Logic LDO voltage feedback input pin; regulates to 1.2V nominal

Logic LDO base drive; open drain of an internal N channel MOSFET

Positive LDO voltage feedback input pin; regulates to 1.2V nominal

Positive LDO base drive; open drain of an internal N channel MOSFET

Enable pin for the chip; high enable; low disabled

Positive supply for all internal circuitry except DRVB

Positive supply for external N channel FET gate drive (DRVB)

Output gate drive of the external fault protection P channel FET; when chip is disabled or when a fault has

been detected, this pin is high

8

FN7318.0

July 12, 2005

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