EL7562(2002) 查看數據表（PDF） - Intersil
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EL7562 Datasheet PDF : 7 Pages
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Technical Brief 423
Design Considerations
Choosing the Component Values
The following requirements are specified for a DC:DC
converter:
• Input voltage range: VIN = 4.5V-5.5V
• Output voltage: VO = 3.3V
• Max output voltage ripple: ∆VO = 50mV
• Output max current: IO = 2A
The following steps briefly outline the steps to choose
components.
1. Choose the feedback resister divider.
The output voltage is decided by:
VOUT
=
0.985
×
1
+
RR-----21-
For VIN = 5V
VOUT
=
0.975
×
1
+
RR-----21-
For VIN = 3.3V
2. Choose the converter switching frequency FS.
FS, inductor L1, output capacitor C7, and EL7562’s
switching loss are closely related. many iterations (or
thermal measurements) may be required before a final
value can be decided.
Please refer to the EL7562 data sheet for the FS vs
COSC curve.
3. Inductor L1.
The EL7562 is internally ramp-compensated. For
optimal operation, the inductor current ripple should be
less than 0.6A.
If ∆IL = 0.5A, then:
L = -(--1-----–-----D-----)---×-----V----O---
∆IL × FS
where:
D = -V-----O---
VIN
Choosing L1 = 4.7µH yields ∆ILMAX = 0.56A. L1 should
also be able to handle DC current of 2A and peak
current of 2.3A at temperature range.
4. Output capacitor C7.
∆VO and ∆IL normally decide C7 value. ∆VO requires
ESR of C7 be less than:
ESR
=
-----∆----V----O-------
∆ILMAX
=
89 m Ω
Double-check the RMS current requirement of the output
capacitor:
∆IC7
=
-∆----I--L---M-----A----X-
12
which is 0.16A. For a capacitor or combination of
capacitors with 89mΩ parallel ESR, it is more than
enough to handle this current.
5. Input capacitors C1 and C2.
If all the AC current is handled by the input capacitors its
RMS current is calculated as:
IIN,rms = [D × (1 – D ) ] × IO
This gives almost 0.99A when D = DMAX. Therefore a
cap with 0.99A current handling capability should be
chosen. However, in case some other capacitor is
sharing current with it, this current requirement can be
reduced.
Layout Considerations
The layout is very important for the converter to function
properly. Power Ground ( ) and Signal Ground ( ) should
be separated to ensure that the high pulse current in the
Power Ground never interferes with the sensitive signals
connected to Signal Ground. They should only be connected
at one point (normally at the negative side of either the input
or output capacitor.)
The trace connected to pin 14 (FB) is the most sensitive
trace. It needs to be as short as possible and in a “quiet”
place, preferably between the PGND and SGND traces.
In addition, the bypass capacitor C3 should be as close to
pins 1 and 3 as possible.
The heat of the chip is mainly dissipated through the PGND
pins. Maximizing the copper area around these pins is
preferable. In addition, a solid ground plane is always helpful
for the EMI performance.
3
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