8173FSZ 查看數據表（PDF） - Intersil
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8173FSZ Datasheet PDF : 14 Pages
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EL8170, EL8173
Typical Performance Curves V+ = +5V, V- = 0V,VCM = +2.5V, VEN = V-, RL = Open, unless otherwise specified. (Continued)
0.70
N = 2000
0.65
0.60
0.55
MAX
MEDIAN
0.70
N = 1000
0.65
0.60
MAX
MEDIAN
0.50
0.45
MIN
0.40
0.35
0.55
MIN
0.50
0.45
0.30
-40 -20 0
20 40 60 80 100 120
TEMPERATURE (°C)
0.40
-40 -20 0
20 40 60 80 100 120
TEMPERATURE (°C)
FIGURE 37. EL8170 - SLEW RATE vs TEMPERATURE,
INPUT ±0.015V @ GAIN + 100
FIGURE 38. EL8173 - SLEW RATE vs TEMPERATURE,
INPUT ±0.015V @ GAIN + 100
Pin Descriptions
EL8170, EL8173
1
PIN NAME
EN
2
IN-
3
IN+
4
V-
5
FB-
8
FB+
7
V+
6
VOUT
EQUIVALENT CIRCUIT
PIN FUNCTION
Circuit 2
Active LOW logic pins. When pulled above 2V, the corresponding channel turns off
and OUT is high impedance. A channel is enabled when pulled below 0.8V. Built-in
pull downs define each EN pin LOW when left floating.
Circuit 1A, Circuit 1B
Circuit 1A, Circuit 1B
High impedance input terminals. EL8170 input circuit is shown in Circuit 1A, and
the EL8173 input circuit is shown in Circuit 1B. EL8173: to avoid offset drift, it is
recommended that the terminals are not overdriven beyond 1V and the input
current must never exceed 5mA.
Circuit 4
Negative supply terminal.
Circuit 1A, Circuit 1B
Circuit 1A, Circuit 1B
High impedance feedback terminals. EL8170 input circuit is shown in Circuit 1A,
and the EL8173 input circuit is shown in Circuit 1B. EL8173: to avoid offset drift, it
is recommended that the terminals are not overdriven beyond 1V and the input
current must never exceed 5mA.
Circuit 4
Positive supply terminal.
Circuit 3
Output Voltage.
IN-
FB-
CIRCUIT 1A
IN-
FB-
V+
IN+
FB+
V-
V+
IN+
FB+
V-
LOGIC
PIN
V+
V-
CIRCUIT 2
V+
OUT
V-
CIRCUIT 3
V+
CAPACITIVELY
COUPLED
ESD CLAMP
V-
CIRCUIT 4
CIRCUIT 1B
10
FN7490.4
February 14, 2008
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