EN5312Q 查看數據表（PDF） - Unspecified
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EN5312Q Datasheet PDF : 13 Pages
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Rev. 0.87 – January 2006
with frequency, bias, and temperature and are not
recommended for switch-mode DC-DC converter
input and output filter applications.
The output capacitance requirement is a minimum
of 10uF. The control loop is designed to be stable
with up to 100uF of total output capacitance.
Capacitance above the 10uF minimum should be
EN5312Q
added if the transient performance is not sufficient
using the 10uF. Enpirion recommends a low ESR
MLCC type capacitor be used. The output capacitor
must use a X5R or X7R dielectric formulation.
Y5V or equivalent dielectric formulations loose
capacitance with frequency, bias, and temperature
and are not recommended for switch-mode DC-DC
converter input and output filter applications
Layout Considerations and Application Circuits
EMI Considerations for Board Layout
Integrated inductor and planar inductor construction
go a long way toward reducing many of the sources
of EMI, both conducted and radiated. However,
care must still be taken to minimize potential
sources of EMI. The package pin-out is carefully
engineered to allow for the optimal layout. Input,
output, and power ground planes are arranged such
that the physical size of the AC current loops can be
minimized and noisy power ground isolated.
1. Single point grounding: To limit AC
current from flowing onto sensitive signal
ground planes it is strongly recommended
that a single point of contact be used for
system ground. The thermal/ground pad
located on the bottom of the package should
be used for this common grounding point.
The PGND pins, pins 3 and 4, are internally
connected to the thermal/ground pad and so
provides for an isolated power ground node
for the input and output filter capacitors.
Connect the input and output filter
capacitors to these ground pins as shown in
figure 7. Do not use these grounds for any
other connections.
(+)
(-)VIN
4.7µF
10µF
VIN
1
VIN
2
GND 3
GND 4
VOUT 5
VOUT 6
AGND
16 VFB
15 VSENSE
14 NC
13 NC
12 NC
11 NC
(-)
VOUT
(+)
Figure 7. Common point grounding schematic.
2. Pins 9, 11, 12, 13 are connected internally
to VDRAIN. Keep all sensitive signal traces
away from these pins.
3. Do not use vias for input and output filter
caps. It is very important that input and
output filter caps be placed on the same side
of the board as the EN5312Q. At
frequencies above 1 MHz, the skin
penetration is too shallow for the AC signals
to pass properly through a via. The AC
currents will instead conduct along the
surface of the planes and potentially couple
noise.
Rev. 0.87 – January 2006
8
www.enpirion.com
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