MAX7000B 查看數據表（PDF） - Altera Corporation

零件编号

产品描述 (功能)

生产厂家

MAX7000B

Programmable Logic Device

Altera Corporation 

MAX 7000B Programmable Logic Device Data Sheet

MAX 7000B devices provide programmable speed/power optimization.

Speed-critical portions of a design can run at high speed/full power,

while the remaining portions run at reduced speed/low power. This

speed/power optimization feature enables the designer to configure one

or more macrocells to operate up to 50% lower power while adding only

a nominal timing delay. MAX 7000B devices also provide an option that

reduces the slew rate of the output buffers, minimizing noise transients

when non-speed-critical signals are switching. The output drivers of all

MAX 7000B devices can be set for 3.3 V, 2.5 V, or 1.8 V and all input pins

are 3.3-V, 2.5-V, and 1.8-V tolerant, allowing MAX 7000B devices to be

used in mixed-voltage systems.

MAX 7000B devices are supported by Altera development systems, which

are integrated packages that offer schematic, text—including VHDL,

Verilog HDL, and the Altera Hardware Description Language (AHDL)—

and waveform design entry, compilation and logic synthesis, simulation

and timing analysis, and device programming. Altera software provides

EDIF 2 0 0 and 3 0 0, LPM, VHDL, Verilog HDL, and other interfaces for

additional design entry and simulation support from other industry-

standard PC- and UNIX-workstation-based EDA tools. Altera software

runs on Windows-based PCs, as well as Sun SPARCstation, and HP 9000

Series 700/800 workstations.

f

For more information on development tools, see the MAX+PLUS II

Programmable Logic Development System & Software Data Sheet and the

Quartus Programmable Logic Development System & Software Data Sheet.

Functional

Description

The MAX 7000B architecture includes the following elements:

■ LABs

■ Macrocells

■ Expander product terms (shareable and parallel)

■ PIA

■ I/O control blocks

The MAX 7000B architecture includes four dedicated inputs that can be

used as general-purpose inputs or as high-speed, global control signals

(clock, clear, and two output enable signals) for each macrocell and I/O

pin. Figure 1 shows the architecture of MAX 7000B devices.

Altera Corporation

5

Share Link: